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Core VLSI

Branch: Electronics and Communication

Topic: Embedded Systems

S.no. Project code Project theme Technology Download
1 TODST-CVLSI01 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic CORE VLSI Download
2 TODST-CVLSI02 A Modified Partial Product Generator for Redundant Binary Multipliers CORE VLSI Download
3 TODST-CVLSI03 Design & Analysis of 16 bit RISC Processor Using low Power Pipelining CORE VLSI Download
4 TODST-CVLSI04 Design and Analysis of Approximate Compressors for Multiplication CORE VLSI Download
5 TODST-CVLSI05 Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics CORE VLSI Download
6 TODST-CVLSI06 Design and implementation of fast floating point multiplier unit CORE VLSI Download
7 TODST-CVLSI07 Area and Frequency optimized 1024 point Radix-2 FFT Processor on FPGA CORE VLSI Download
8 TODST-CVLSI08 Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata CORE VLSI Download
9 TODST-CVLSI09 Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier CORE VLSI Download
10 TODST-CVLSI10 Design of Area and Power Efficient Digital FIR Filter Using Modified MAC Unit CORE VLSI Download
11 TODST-CVLSI11 Design of Low Power and High-Speed Carry Select Adder Using Brent-Kung Adder CORE VLSI Download
12 TODST-CVLSI12 Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications CORE VLSI Download
13 TODST-CVLSI13 FPGA Implementation of Scalable Microprogrammed FIR Filter Architectures using Wallace Tree and Vedic Multipliers CORE VLSI Download
14 TODST-CVLSI14 FPGA Implementation of Vedic Floating Point Multiplier

 

CORE VLSI Download
15 TODST-CVLSI15 FPGA Realization and Performance Evaluation of Fixed-Width Modified Baugh-Wooley Multiplier CORE VLSI Download
16 TODST-CVLSI16 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels CORE VLSI Download
17 TODST-CVLSI17 FPGA based Scalable Fixed Point QRD core using Dynamic Partial Reconfiguration CORE VLSI Download
18 TODST-CVLSI18 Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA CORE VLSI Download
19 TODST-CVLSI19 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication CORE VLSI Download
20 TODST-CVLSI20 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications CORE VLSI Download
21 TODST-CVLSI21 A High-Speed FPGA Implementation of an RSD-Based ECC Processor CORE VLSI Download
22 TODST-CVLSI22 Analysis of Ternary Multiplier using Booth Encoding Technique CORE VLSI Download
23 TODST-CVLSI23 A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM CORE VLSI Download
24 TODST-CVLSI24 HMFPCC: – Hybrid-Mode Floating Point Conversion Co-processor CORE VLSI Download
25 TODST-CVLSI25 On the Analysis of Reversible Booth’s Multiplier CORE VLSI Download
26 TODST-CVLSI26 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding CORE VLSI Download
27 TODST-CVLSI27 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations CORE VLSI Download
28 TODST-CVLSI28 Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI CORE VLSI Download
29 TODST-CVLSI29 Advanced Low Power RISC Processor Design using MIPS Instruction Set CORE VLSI Download
30 TODST-CVLSI30 RTL Implementation for AMBA ASB APB Protocol at System on Chip Level

 

 

CORE VLSI Download
31 TODST-CVLSI31 Run-time reconfigurable multi-precision floating point multiplier design for high-speed, low-power applications CORE VLSI Download
32 TODST-CVLSI32 Technology Optimized Fixed-Point Bit-Parallel Multiplier for LUT-based FPGAs CORE VLSI Download
33 TODST-CVLSI33 Truncated ternary multipliers CORE VLSI Download
34 TODST-CVLSI34 An efficient floating point multiplier design for high-speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm CORE VLSI Download

 

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