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VLSI Back end

Branch: Electronics and Communication

Topic: VLSI Back-end

S.no. Project code Project theme Technology Download
1 TODST-VLSIBE01 Voltage mode Implementaion of Highly Accurate analog Multiplier circuit Back end Download
2 TODST-VLSIBE02 Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme Back end Download
3 TODST-VLSIBE03 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing Back end Download
4 TODST-VLSIBE04 Digital-to-Time Converter using SET in HSPICE Back end Download
5 TODST-VLSIBE05 Design of high speed ternary full adder and three-input XOR circuits using CNTFETs Back end Download
6 TODST-VLSIBE06 Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates Back end Download
7 TODST-VLSIBE07 Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata Back end Download
8 TODST-VLSIBE08 Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell Back end Download
9 TODST-VLSIBE09 A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process Back end Download
10 TODST-VLSIBE10 A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist Back end Download
11 TODST-VLSIBE11 A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology Back end Download
12 TODST-VLSIBE12 A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links Back end Download
13 TODST-VLSIBE13 A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique Back end Download
14 TODST-VLSIBE14 An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells Back end Download
15 TODST-VLSIBE15 Read Performance: The Newest Barrier in Scaled STT-RAM Back end Download
16 TODST-VLSIBE16 On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ Back end Download
17 TODST-VLSIBE17 High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors Back end Download
18 TODST-VLSIBE18 High-Frequency CMOS Active Inductor: Design Methodology and Noise Analysis Back end Download
19 TODST-VLSIBE19 Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model Back end Download
20 TODST-VLSIBE20 A CMOS PWM Transceiver Using Self-Referenced Edge Detection Back end Download
21 TODST-VLSIBE21 Achieving Power Reduction by using Multi-Bit Flip-Flop Back end Download
22 TODST-VLSIBE22 Implementation of low power multi shaped CMOS fuzzier circuit Back end Download

 

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