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Branch: Electrical Engineering

Topic: Power Electronics Project code Project theme Technology
1 ICDST-AD01 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage VLSI
2 ICDST-AD02 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS VLSI
3 ICDST-AD03 A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures VLSI
4 ICDST-AD04 A 2.4–3.6-GHz Wideband Sub harmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique VLSI
5 ICDST-AD05 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging VLSI
6 ICDST-AD06 A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network VLSI
7 ICDST-AD07 A 65-nm CMOS Constant Current Source With Reduced PVT Variation VLSI
8 ICDST-AD08 A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing VLSI
9 ICDST-AD09 A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression VLSI
10 ICDST-AD10 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding VLSI
11 ICDST-AD01 A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy VLSI
12 ICDST-AD02 A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission VLSI
13 ICDST-AD03 A High-Speed and Power-Efficient Voltage Level VLSI
14 ICDST-AD04 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits VLSI
15 ICDST-AD05 A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs VLSI
16 ICDST-AD06 A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption VLSI
17 ICDST-AD07 Adaptive Multi-bit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication VLSI
18 ICDST-AD08 An All-MOSFET Sub-1-V Voltage Reference With a −51-dB PSR up to 60 MHz VLSI
19 ICDST-AD09 An FPGA-Based Hardware Accelerator for Traffic Sign Detection VLSI
20 ICDST-AD10 Anti-wear Leveling Design for SSDs With Hybrid ECC capability VLSI
21 ICDST-AD01 Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications VLSI
22 ICDST-AD02 COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits VLSI
23 ICDST-AD03 Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application VLSI
24 ICDST-AD04 Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture VLSI
25 ICDST-AD05 Delay Analysis for Current Mode Threshold Logic Gate Designs VLSI
26 ICDST-AD06 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers VLSI
27 ICDST-AD07 Efficient Designs of Multi-ported Memory on FPGA VLSI
28 ICDST-AD08 Efficient Soft Cancelation Decoder Architectures for Polar Codes VLSI
29 ICDST-AD09 Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations VLSI
30 ICDST-AD10 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology VLSI
31 ICDST-AD01 Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems VLSI
32 ICDST-AD02 ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware VLSI
33 ICDST-AD03 Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm VLSI
34 ICDST-AD04 Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA VLSI
35 ICDST-AD05 FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over GF(2m) and Their Applications in Trinomial Multipliers VLSI
36 ICDST-AD06 Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares VLSI
37 ICDST-AD07 High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA VLSI
38 ICDST-AD08 High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations VLSI
39 ICDST-AD09 High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder VLSI
40 ICDST-AD10 Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs VLSI
41 ICDST-AD01 Hybrid LUT/Multiplexer FPGA Logic Architectures VLSI
42 ICDST-AD02 Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis VLSI
43 ICDST-AD03 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition VLSI
44 ICDST-AD04 Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non binary LDPC Codes Over Subfields VLSI
45 ICDST-AD05 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique VLSI
46 ICDST-AD06 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding VLSI
47 ICDST-AD07 Multicast-Aware High-Performance Wireless Network-on-Chip Architectures VLSI
48 ICDST-AD08 On Micro architectural Mechanisms for Cache Wear out Reduction VLSI
49 ICDST-AD09 Probability-Driven Multibit Flip-Flop Integration With Clock Gating VLSI
50 ICDST-AD10 Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design VLSI
51 ICDST-AD01 Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction VLSI
52 ICDST-AD02 Resource-Efficient SRAM-based Ternary Content Addressable Memory VLSI
53 ICDST-AD03 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing VLSI
54 ICDST-AD04 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST VLSI
55 ICDST-AD05 Scalable Device Array for Statistical Characterization of BTI-Related Parameters VLSI
56 ICDST-AD06 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template VLSI
57 ICDST-AD07 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication VLSI
58 ICDST-AD08 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations VLSI
59 ICDST-AD09 Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map VLSI
60 ICDST-AD10 Temporarily Fine-Grained Sleep Technique for Near- and Sub threshold Parallel Architectures VLSI
61 ICDST-AD01 Temporarily Fine-Grained Sleep Technique for Near- and Sub threshold Parallel Architectures VLSI
62 ICDST-AD02 Variation Resilient Power Sensor With an 80-ns Response Time for Fine-Grained Power Management VLSI
63 ICDST-AD03 VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding VLSI
64 ICDST-AD04 Write-Amount-Aware Management Policies for STT-RAM Caches VLSI