VLSI PROJECTS (2019-20)
Low Power VLSI
| S.NO | TITLES | Download |
| DST TO LPV 01 | Low-power and fast full adder by exploring new xor and xnor gates | |
| DST TO LPV 02 | Low-power and fast full adder by exploring new xor and xnor gates | |
| DST TO LPV 03 | Design of area efficient and low power 4-bit multiplier based on full- swing gdi technique | |
| DST TO LPV 04 | Parametric and functional degradation analysis of complete 14-nm finfet sram | |
| DST TO LPV 05 | Power efficient and reliable nonvolatile tcam with hi-pfo and semi-complementary driver | |
| DST TO LPV 06 | A low power and high speed voltage level shifter based on a regulated cross coupled pull up network | |
| DST TO LPV 07 | Hybrid logical effort for hybrid logic style full adders in multistage structures | |
| DST TO LPV 08 | A 12t low-power standard-cell based sram circuit for ultra-low-voltage operations | |
| DST TO LPV 09 | Analysis of adiabatic flip-flops for ultra low power applications | |
| DST TO LPV 010 | Power reduction in domino logic using clock gating in 16nm cmos technology | |
| DST TO LPV 011 | Design of area efficient and low power 4-bit multiplier based on full swing gdi technique | |
| DST TO LPV 012 | Design of low power ecrl based power gated 4:2 compressor |
