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VLSI Design Based ME/M.tech Projects

Sno

Projects List

IEEE

1. Low-Power and Area-Efficient Carry Select Adder

2012

2. Platform-Independent Customizable UART Soft-Core

2012

3. Accumulator Based 3-Weight Pattern Generation

2012

4. An efficient FPGA implementation of the Advanced Encryption Standard algorithm

2012

5. Implementation of a Flexible and Synthesizable FFT Processor

2012

6. An On-Chip Delay Measurement Technique Using Signature Registers For Small-Delay Defect Detection

2012

7. Period Extension And Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG

2012

8. Single Cycle Access Structure For Logic Test

2012

9. A   Lightweight High-Performance Fault Detection Scheme For The Advanced Encryption Standard Using Composite Fields

2012

10. A Low-Power Single-Phase Clock Multiband Flexible Divider

2012

11. ON MODULO 2n + 1 ADDER DESIGN

2012

12. Measurement And Evaluation Of Power Analysis Attacks On Asynchronous S-Box

2012

13. Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures

2012

14. Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics

2012

15. Design and Implementation of a High Performance Multiplier using HDL

2012

16. An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC

2011

17. Reliable and Cost Effective Anti-coll ision Technique for RFID UHF Tag

2011

18. Ddr3 Based Lookup Circuit For High  Performance  Network Processing

2011

19. Design And Implementation Of High Performance AHB Reconfigurable Arbiter For On-Chip Bus Architecture

2011

20. Self-Immunity Technique to Improve Register File Integrity against Soft Errors

2011

21. 16-Bit RISC Processor Design For Convolution Application

2011

22. Radix-8 Booth Encoded Modulo 2n-1 Multipliers With Adaptive Delay For High Dynamic Range Residue Number System

2011

23. A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC)

2011

24. High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree

2011

25. An Efficient Implementation of Floating Point Multiplier

2011

26. Reducing the Computation Time in (Short Bit-Width) Two’s Complement Multipliers

2011

27. Design and Characterization of Parallel Prefix Adders using FPGAs

2011

28. A New VLSI Architecture Of Parallel Multiplier Accumulator Based On Radix-4 Modified Booth Algorithm.

2010

29. An Efficient Architecture For 3-D Discrete Wavelet Transform

2010

30. Low Power ALU Design By Ancient Mathematics

2010

31. Design Of On-Chip Bus With OCP Interface

2010

32. An Efficient Architecture For 2-D Lifting-Based Discrete Wavelet Transform

2009

33. Multiplication Acceleration Through Twin Precision

2009

34. Efficient FPGA Implementation Of Convolution

2009

35. Implementation Of FFT/IFFT Blocks For OFDM

2009

One Response so far.

  1. kindly us me if you provide seminars or workshops on “Android” in engineering colleges of Bhopal.Aslo kindly inform us about any other training programs that you could provide.

    Thanks and regards.

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