VLSI
Branch: Electronics and Communication
Topic: VLSI projects
| S.NO | TITLES |
DOMAIN |
| VLSI | ||
| DST TO VLSI 01 | Approximate Quaternary Addition with the Fast Carry Chains of FPGAs | |
| DST TO VLSI 02 | A Low-Power Configurable Adder for Approximate Applications | |
| DST TO VLSI 03 | A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design | |
| DST TO VLSI 04 | Optimizing Power-Accuracy trade-off in Approximate Adders | |
| DST TO VLSI 05 | A Simple Yet Efficient Accuracy- Configurable Adder Design | |
| DST TO VLSI 06 | A Low Power CMOS Temperature Sensor Frontend for RFID Tags | |
| DST TO VLSI 07 | Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability | |
| DST TO VLSI 08 | A Low-Power Yet High-Speed Configurable Adder for Approximate Computing | |
| DST TO VLSI 09 | Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error- Tolerant Applications | |
| DST TO VLSI 10 | Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications | |
| DST TO VLSI 11 | A Double Error Correction Code for 32-bit Data Words with Efficient Decoding | |
| DST TO VLSI 12 | An Efficient VLSI Architecture for Convolution Based DWT Using MAC | |
| DST TO VLSI 13 | High Speed Power Efficient Carry Select Adder Design | |
| DST TO VLSI 14 | Design of Majority Logic (ML) Based Approximate Full Adders | |
| DST TO VLSI 15 | High Performance VLSI Architecture for Transpose Form FIR Filter using Integrated Module | |
| DST TO VLSI 16 | Fault-tolerant design and analysis of QCA based circuits | |
| DST TO VLSI 17 | Unbiased Rounding for HUB Floating-point Addition | |
| DST TO VLSI 18 | Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error | |
| DST TO VLSI 19 | Combined Pseudo-Exhaustive and Deterministic Testing of Array Multipliers | |
| DST TO VLSI 20 | Nonlinear Binary Codes and Their Utilization for Test | |
| DST TO VLSI 21 | A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher | |
| DST TO VLSI 22 | A Novel approach for design of Real Time Traffic Control System using Verilog HDL | |
| DST TO VLSI 23 | An efficient way of implementing high speed 4-Bit advanced multipliers in FPGA | |
| DST TO VLSI 24 | An Inter-Layer Interconnect BIST Solution for Monolithic 3D ICs | |
| DST TO VLSI 25 | Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications | |
| DST TO VLSI 26 | Built-in Test for Hidden Delay Faults | |
| DST TO VLSI 27 | Design and Verilog HDL Implementation of Carry Skip Adder Using Kogge-Stone Tree Logic | |
| DST TO VLSI 28 | High Speed Efficient Multiplier Design using Reversible Gates | |
| DST TO VLSI 29 | High-Performance NTT Architecture for Large Integer Multiplication | |
| DST TO VLSI 30 | Inexact Arithmetic Circuits for Energy Efficient loT Sensors Data Processing | |
| DST TO VLSI 31 | A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test | |
| DST TO VLSI 32 | A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits | |
| DST TO VLSI 33 | Automotive functional safety assurance by post with sequential observation | |
| DST TO VLSI 34 | Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation | |
| DST TO VLSI 35 | Logic BIST with Capture-per-Clock Hybrid Test Points | |
| DST TO VLSI 36 | Flexible Architecture of Memory BISTs | |
| DST TO VLSI 37 | Efficient Implementations of 4-Bit Burst Error Correction for Memories | |
| DST TO VLSI 38 | Towards Efficient Modular Adders based on Reversible Circuits | |
| DST TO VLSI 39 | Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder | |
| DST TO VLSI 40 | Design, Implementation and Verification of 32-Bit ALU with VIO | |
| DST TO VLSI 41 | All Optical Design of Hybrid Adder Circuit Using Terahertz Optical Asymmetric Demultiplexer | |
| DST TO VLSI 42 | A Novel Reversible Synthesis of Array Multiplier | |
| DST 1CP VLSI 43 | Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter | |
| DST 1CP VLSI 44 | FIR filter design based on FPGA | |
| DST 1CP VLSI 45 | An Approach to LUT Based Multiplier for Short Word Length DSP Systems | |
| DST 1CP VLSI 46 | FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications | |
| DST 1CP VLSI 47 | Chip Design for Turbo Encoder Module for In-Vehicle System | |
| DST 1CP VLSI 48 | BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA | |
| DST 1CP VLSI 49 | A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA) | |
| DST 1CP VLSI 50 | Application of Bit-Serial Arithmetic Units for FPGA Implementation of Convolutional Neural Networks | |
| DST 1CP VLSI 51 | Design and simulation of CRC encoder and decoder using VHDL/verilog | |
| DST 1CP VLSI 52 | Time to Digital Converter Based on a Ring Oscillator with Even Number of Non- Inverting Elements | |
| DST 1CP VLSI 53 | A Channel-Sharable Built-In Self-Test Scheme for Multi-Channel DRAMs | |
| DST 1CP VLSI 54 | Random Number Generation with LFSR Based Stream Cipher Algorithms | |
| DST 1CP VLSI 53 | Characterization of Clock Buffers for On-Chip Inter-Circuit Communication in Xilinx FPGAs | |
| DST 1CP VLSI 53 | Design and Implementation of the Algorithm for RB Multiplication to Derive High-Throughput Digit-Serial Multipliers | |
| DST 1CP VLSI 53 | FPGA Realization of Speech Encryption Based on Modified Chaotic Logistic Map | |
| DST 1CP VLSI 53 | VLSI Implementation of Channel Estimation for Millimeter Wave Beam forming Training | |
| DST 1CP VLSI 53 | Heuristic based Majority/Minority Logic Synthesis for Emerging Technologies | |
| DST 1CP VLSI 53 | A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation | |
| DST 1CP VLSI 53 | Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression | |
| DST 1CP VLSI 53 | A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA using Chisel HCL | |
| DST 1CP VLSI 53 | Area and Performance Evaluation of Central DMA Controller in Xilinx Embedded FPGA Designs | |
| DST 1CP VLSI 53 | Design of Low Power Multiplierless Linear-Phase FIR Filters | |
| DST 1CP VLSI 53 | Algorithm for Constructing Minimal Representations of Multiple-output Boolean Functions in The Reversible Logic Circuits | |
| DST 1CP VLSI 53 | FPGA Implementation of Matrix-Vector Multiplication Using Xilinx System Generator | |
| DST 1CP VLSI 53 | Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata | |
| DST 1CP VLSI 53 | Design of Power and Area Efficient Approximate Multipliers | |
| DST 1CP VLSI 53 | Low-Power Approximate MAC Unit | |
| DST 1CP VLSI 53 | Efficient Design-for-Test Approach for Networks-on-Chip | |
| DST 1CP VLSI 53 | Integrating BIST techniques for on-line SoC testing | |
| DST 1CP VLSI 53 | A Reliable Strong PUF Based on Switched-Capacitor Circuit | |
| DST 1CP VLSI 53 | Reducing the Hardware Complexity of a Parallel Prefix Adders | |
| DST 1CP VLSI 53 | Research and implementation of hardware algorithms for multiplying binary numbers | |
| DST 1CP VLSI 53 | Division circuits using reversible logic gates | |
| DST 1CP VLSI 53 | Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion | |
| DST 1CP VLSI 53 | Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates | |
| DST 1CP VLSI 53 | Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder | |
| DST 1CP VLSI 53 | Positive Feedback Symmetric Adiabatic Logic against Differential Power Attack | |
| DST 1CP VLSI 53 | Soft-Error Tolerant Design in Near-Threshold-Voltage Computing | |
| DST 1CP VLSI 53 | Stateful Memristor-Based Search Architecture | |
| DST 1CP VLSI 53 | CMOS circuit techniques for Mm –wave communications | |
| DST 1CP VLSI 53 | Approximate Fully Connected Neural Network Generation | |
| DST 1CP VLSI 53 | Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique | |
| DST 1CP VLSI 53 | FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks | |
| DST 1CP VLSI 53 | Analysis of Optimization Techniques for Low Power VLSI Design | |
| DST 1CP VLSI 53 | Low Power GDI ALU Design with Mixed Logic Adder Functionality | |
| DST 1CP VLSI 53 | Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications | |
| DST 1CP VLSI 53 | Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis | |
| DST 1CP VLSI 53 | Fractional-Order Differentiators and Integrators with Reduced Circuit Complexity | |
| DST 1CP VLSI 53 | High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop | |
| DST 1CP VLSI 53 | A Low-Power High-Speed Comparator for Precise Applications | |
| DST 1CP VLSI 53 | High-Density SOT-MRAM Based on Shared Bitline Structure | |
| DST 1CP VLSI 53 | Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM | |
| DST 1CP VLSI 53 | Enabling Fast Process Variation and Fault Simulation Through Macromodelling of Analog Components | |
| DST 1CP VLSI 53 | A SEU/MBU Tolerant SRAM Bit Cell Based on Multi-Input Gate | |
| DST 1CP VLSI 53 | Design of low power magnitude comparator | |
| DST 1CP VLSI 53 | Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications | |
| DST 1CP VLSI 53 | High-performance engineered gate transistor-based compact digital circuits | |
| DST 1CP VLSI 53 | Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation |
INSIGHT
