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VLSI

Branch: Electronics and Communication

Topic: VLSI

S.no. Project code Project theme Technology Download
1 ICDST-VLSI01 Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing VLSI Download
2 ICDST-VLSI02 An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC VLSI Download
3 ICDST-VLSI03 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block VLSI Download
4 ICDST-VLSI04 High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule VLSI Download
5 ICDST-VLSI05 Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks VLSI Download
6 ICDST-VLSI06 A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme VLSI Download
7 ICDST-VLSI07 Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM VLSI Download
8 ICDST-VLSI08 A 65 nm Cryptographic Processor for High Speed Pairing Computation VLSI Download
9 ICDST-VLSI09 VLSI Design for SVM-Based Speaker Verification System VLSI Download
11 ICDST-VLSI11 11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids VLSI Download
12 ICDST-VLSI12 A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT VLSI Download
13 ICDST-VLSI13 A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

 

 

VLSI Download
14 ICDST-VLSI14 A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks VLSI Download
15 ICDST-VLSI15 A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification VLSI Download
16 ICDST-VLSI16 A Synergetic Use of Bloom Filters for Error Detection and Correction VLSI Download
17 ICDST-VLSI17 A 0.45-V, 14.6-nW CMOS Subthres hold Voltage Reference With No Resistors and No BJTs VLSI Download
18 ICDST-VLSI18 An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications VLSI Download
19 ICDST-VLSI19 An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats VLSI Download
20 ICDST-VLSI20 Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover VLSI Download
21 ICDST-VLSI21 Economizing TSV Resources in 3-D Network-on-Chip Design VLSI Download
22 ICDST-VLSI22 Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs VLSI Download
23 ICDST-VLSI23 Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications VLSI Download
24 ICDST-VLSI24 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels VLSI Download
25 ICDST-VLSI25 Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores VLSI Download
26 ICDST-VLSI26 Novel VLSI Architecture for Real Time  Medical Image Segmentation VLSI Download
27 ICDST-VLSI27 Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels VLSI Download
28 ICDST-VLSI28 Partially Parallel Encoder Architecture for Long Polar Codes VLSI Download
29 ICDST-VLSI29 Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs VLSI Download
30 ICDST-VLSI30 Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures VLSI Download
31 ICDST-VLSI31 An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs VLSI Download
32 ICDST-VLSI32 Drowsy Driver Detection using Representation Learning VLSI Download
33 ICDST-VLSI33 Information Hiding as a Challenge for Malware Detection VLSI Download
34 ICDST-VLSI34 Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit VLSI Download
35 ICDST-VLSI35 Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology VLSI Download
36 ICDST-VLSI36 Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication VLSI Download
37 ICDST-VLSI37 VLSI Computational Architectures for the Arithmetic Cosine Transform VLSI Download
38 ICDST-VLSI38 A New Data Transfer Method via Signal-Rich-Art Code Images Captured by Mobile Devices VLSI Download
39 ICDST-VLSI39 A Low-Power Edge Detection Image Sensor Based on Parallel Digital Pulse Computation VLSI Download
40 ICDST-VLSI40 WIFI neighbor awareness networking VLSI Download
41 ICDST-VLSI41 A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems VLSI Download
42 ICDST-VLSI42 A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation VLSI Download
43 ICDST-VLSI43 A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation VLSI Download
44 ICDST-VLSI44 All Digital Energy Sensing for Minimum Energy Tracking VLSI Download
45 ICDST-VLSI45 Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secu re Integrated Circuits VLSI Download
46 ICDST-VLSI46 Design of Modified Sec ond-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics VLSI Download
47 ICDST-VLSI47 Drowsy Driver Detection using Representation Learning VLSI Download
48 ICDST-VLSI48 Energy and Area Efficient Three-Input XOR/ XNORs With Systematic Cell Design Methodology VLSI Download
49 ICDST-VLSI49 Fast Design Space Exploration using Vivado HLS: Non-Binary LDPC Decoders VLSI Download
50 ICDST-VLSI50 Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint VLSI Download
51 ICDST-VLSI51 Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application VLSI Download
52 ICDST-VLSI52 Knowledge-Based Neural Network Model for FPGA Logical Architecture Development VLSI Download
53 ICDST-VLSI53 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication VLSI Download
54 ICDST-VLSI54 On System-on-Chip Testing Using Hybrid Test Vector Compression VLSI Download
55 ICDST-VLSI55 Performance Analysis and Optimization for Homogenous Multi-core System based on 3D Torus Network on Chip VLSI Download
56 ICDST-VLSI56 Secure Binary Image Steganography Based on Minimizing the Distortion on the Texture VLSI Download
57 ICDST-VLSI57 Star-Type Architecture with Low Transmission Latency for a 2D Mesh NOC VLSI Download
58 ICDST-VLSI58 Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product VLSI Download
59 ICDST-VLSI59 Unified VLSI architecture for photo core transform used in JPEG XR VLSI Download
60 ICDST-VLSI60 A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors VLSI Download
61 ICDST-VLSI61 A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator VLSI Download
62 ICDST-VLSI62 A Micro-Power Two-Step Incremental Analog-to-Digital Converter VLSI Download

 

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