Core vlsi BE

Branch: VLSI

Topic: CORE VLSI BE

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S.No	TITLES	DOMAIN	DOWNLOAD
	CORE VLSI
DST TO C 01	Approximate Quaternary Addition with the Fast Carry Chains of FPGAs	CORE VLSI
DST TO C 02	A Low-Power Configurable Adder for Approximate Applications	CORE VLSI
DST TO C 03	A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design	CORE VLSI
DST TO C 04	A Low-Power Yet High-Speed Configurable Adder for Approximate Computing	CORE VLSI
DST TO C 05	A Simple Yet Efficient Accuracy- Configurable Adder Design	CORE VLSI
DST TO C 06	Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design	CORE VLSI
DST TO C 07	Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers	CORE VLSI
DST TO C 08	A Cost-Effective Self-Healing Approach for Reliable Hardware Systems	CORE VLSI
DST TO C 09	Approximate Sum-of-Products Designs Based on Distributed Arithmetic	CORE VLSI
DST TO C 010	Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications	CORE VLSI
DST TO C 011	Design, Evaluation and Application of Approximate High-Radix Dividers	CORE VLSI
DST TO C 012	Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors	CORE VLSI
DST TO C 013	Enhancing Fundamental Energy Limits of Field-Coupled Nano computing Circuits	CORE VLSI
DST TO C 014	Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors	CORE VLSI
DST TO C 015	Inexact Arithmetic Circuits for Energy Efficient IOT Sensors Data Processing	CORE VLSI
DST TO C 016	Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability	CORE VLSI
DST TO C 017	Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system	CORE VLSI
DST TO C 018	On the Difficulty of Inserting Trojans in Reversible Computing Architectures	CORE VLSI
DST TO C 019	Optimizing Power-Accuracy trade-off in Approximate Adders	CORE VLSI
DST TO C 020	Power Efficient Approximate Booth Multiplier	CORE VLSI
DST TO C 021	Reducing the Hardware Complexity of a Parallel Prefix Adder	CORE VLSI
DST TO C 022	Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder	CORE VLSI
DST TO C 023	Towards Efficient Modular Adders based on Reversible Circuits	CORE VLSI
DST TO C 024	A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier	CORE VLSI
DST TO C 025	Research and implementation of hardware algorithms for multiplying binary numbers	CORE VLSI
DST TO C 026	Efficient Design for Fixed-Width Adder-Tree	CORE VLSI
DST TO C 027	Architecture Generator for Type-3 Unum Posit Adder/Sub tractor	CORE VLSI
	COMMUNICATION
DST TO C 01	Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications	COMMUNICATION
DST TO C 02	A Single and Adjacent Error Correction Code for fast Decoding of Critical Bits	COMMUNICATION
DST TO C 03	Efficient Implementations of 4-Bit Burst Error Correction for Memories	COMMUNICATION
DST TO C 04	Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction	COMMUNICATION
DST TO C 05	Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design	COMMUNICATION
DST TO C 06	A Double Error Correction Code for 32-bit Data Words with Efficient Decoding	COMMUNICATION
DST TO C 07	Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields	COMMUNICATION
DST TO C 08	An Efficient VLSI Architecture for Convolution Based DWT Using MAC	COMMUNICATION
DST TO C 09	Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method	COMMUNICATION
DST TO C 010	Reconfigurable Decoder for LDPC and Polar Codes	COMMUNICATION
DST TO C 011	Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs	COMMUNICATION
DST TO C 012	Design and simulation of CRC encoder and decoder using VHDL	COMMUNICATION
	DIGITAL SIGNAL PROCESSING
DST TO C 01	An Efficient FPGA Implementation of HEVC Intra Prediction	DIGITAL SIGNAL PROCESSING
DST TO C 02	An Area Efficient 1024-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators	DIGITAL SIGNAL PROCESSING
DST TO C 03	Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic	DIGITAL SIGNAL PROCESSING