VLSI low power
| S.No | Project Name | IEEE Year |
| DST KT C 01 | VLSI Design Of Low-Cost And High-Precision Fixed-Point Reconfigurable FFT Processors | |
| DST KT C 02 | Unbiased Rounding for HUB Floating-point Addition | |
| DST KT C 03 | A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design | |
| DST KT C 04 | Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction | |
| DST KT C 05 | A Low-Power Yet High-Speed Configurable Adder for Approximate Computing | |
| DST KT C 06 | The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA | |
| DST KT C 07 | Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers | |
| DST KT C 08 | Efficient Modular Adders based on Reversible Circuits | |
| DST KT C 09 | Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption | |
| DST KT C 010 | Design of 5 port router for network on chip using FPGA | |
| DST KT C 011 | Design And Implementation Of A Novel PRPG for Low Power Applications | |
| DST KT C 012 | Design of MAC Unit For DSP Applications Using Verilog HDL | |
| DST KT C 013 | Floating-Point Butterfly Architecture Based On Multi Operand Adders | |
| DST KT C 014 | VLSI Architecture For Montgomery Modular Multiplication Algorithm By Using Pasta Adder | |
| DST KT C 015 | Pre encoded Multiplier Architecture Based On NR4SD Encoding Technique For DSP Applications | |
| DST KT C 016 | Design And Implementation Of High Speed Accelerator Using Carry Save Adder | |
| DST KT C 017 | A Transparent Test Technique For Detection Of Faults In FIFO Buffers Of NOC Routers | |
| DST KT C 018 | Design Of 16-Bit Multiplier Using Modified Gate Diffusion Input Logic | |
| DST KT C 019 | An Optimized Implementation Of IEEE-754 Floating Point Multiplier For DSP Applications | |
| DST KT C 020 | Efficient Architecture For Processing Of Two Independent Data Streams Using Radix-2 FFT | |
| DST KT C 021 | High Throughput DA-Based Fir Filter For FPGA Implementation | |
| DST KT C 022 | Low Power And Area Efficient Carry Select Adder With Binary To Excess-1 Converter | |
| DST KT C 023 | VLSI Design Of High Speed Vedic Multiplier For FPGA Implementation | |
| DST KT C 015 | A Review On Power Optimized TPG Using LP-LFSR For Low Power BIST | |
| DST KT C 025 | FPGA Based Hardware Implementation Of AES Rijndael Algorithm For Encryption And Decryption. | |
| DST KT C 026 | A Modified Partial Product Generator For Redundant Binary Multipliers | |
| DST KT C 027 | Pipeline And Parallel Processor Architecture For Fast Computation Of 3D-DWT Using Modified Lifting Scheme | |
| DST KT C 028 | Hybrid LUT/Multiplexer FPGA Logic Architectures | |
| DST KT C 029 | A Synergetic Use Of Bloom Filters For Error Detection And Correction | |
| DST KT C 030 | Fault Tolerant Parallel Filters Based On Error Correction Codes | |
| DST KT C 031 | High-Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations |
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| DST KT C 032 | Recursive Approach To The Design of a Parallel Self-Timed Adder | |
| DST KT C 033 | Low Delay Single Symbol Error Correction Codes Based On Reed Solomon Codes | |
| Back End Design | ||
| DST KT C 034 | Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates | |
| DST KT C 035 | Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder | |
| DST KT C 036 | Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders. | |
| DST KT C 037 | Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design. | |
| DST KT C 038 | A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. | |
| DST KT C 039 | Low power 6T SRAM design | |
| DST KT C 040 | Algorithm And Architecture For A Low-Power Content-Addressable Memory Based On Sparse Clustered Networks | |
Branch: Electronics and Communication
Topic: VLSI Low Power
| S.no. | Project code | Project theme | Technology | Download |
| 1 | TODST-VLSILP01 | A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT | DSP | |
| 2 | TODST-VLSILP02 | A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications | DSP | |
| 3 | TODST-VLSILP03 | An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR for Multistandard DUCInterpolation Filter | DSP | |
| 4 | TODST-VLSILP04 | Obfuscating DSP Circuits via High-Level Transformations | DSP | |
| 5 | TODST-VLSILP05 | Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing | DSP | |
| 6 | TODST-VLSILP06 | OptimizedApproach of Sobel Edge Detection Technique Using Xilinx System Generator | Image processing | |
| 7 | TODST-VLSILP07 | Reconfigurable Architecture of Adaptive Median Filter – An FPGA Based Approach for Impulse Noise Suppression | Image processing | |
| 8 | TODST-VLSILP08 | High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis | Image processing | |
| 9 | TODST-VLSILP09 | GFCG: Glitch Free Combinational Clock Gating Approach in Nanometer VLSI Circuits | LOW POWER | |
| 10 | TODST-VLSILP10 | Low Power Compressor Based MAC Architecture for DSP Applications | LOW POWER | |
| 11 | TODST-VLSILP11 | Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing | LOW POWER | |
| 12 | TODST-VLSILP12 | Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames
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LOW POWER | |
| 13 | TODST-VLSILP13 | Power Optimization of Communication System Using Clock Gating Technique | LOW POWER | |
| 14 | TODST-VLSILP14 | Low-Power Programmable PRPG With Test Compression Capabilities | LOW POWER | |
| 15 | TODST-VLSILP15 | Design and Synthesis of Bandwidth Efficient QPSK Modulator for Low Power VLSI Design | LOW POWER | |
| 16 | TODST-VLSILP16 | A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique | LOW POWER | |
| 17 | TODST-VLSILP17 | Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO | LOW POWER | |
| 18 | TODST-VLSILP18 | TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors | LOW POWER | |
| 19 | TODST-VLSILP19 | A Novel Realization of Reversible LFSR for its Application in Cryptography | VLSI | |
| 20 | TODST-VLSILP20 | Preemptive Built-In Self-Test for In-Field Structural Testing | VLSI | |
| 21 | TODST-VLSILP21 | Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment | VLSI | |
| 22 | TODST-VLSILP22 | Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures | VLSI | |
| 23 | TODST-VLSILP23 | Multiplexer based High Throughput S-box for AES Application | VLSI | |
| 15 | TODST-VLSILP15 | Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set | VLSI | |
| 25 | TODST-VLSILP25 | A Method of One-Pass Seed Generation for LFSR-Based Deterministic/Pseudo-Random Testing of Static Faults | VLSI | |
| 26 | TODST-VLSILP26 | Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL | VLSI |
INSIGHT
