TRANSISTOR LOGIC

VLSI PROJECTS (2019-18)

Transistor Logic

S.NO	TITLES	Download
DST TO TL 01	Design of area-efficient and highly reliable rhbd 10t memory cell for aerospace applications
DST TO TL 02	Low-power and fast full adder by exploring new xor and xnor gates
DST TO TL 03	Radiation-hardened 14t sram bitcell with speed and power optimized for space application
DST TO TL 04	A very compact cmos analog multiplier for application in cnn synapses
DST TO TL 05	Counter based low power, low latency wallace tree multiplier using gdi technique for on-chip digital filter applications
DST TO TL 06	Counter based low power, low latency wallace tree multiplier using gdi technique for on-chip digital filter applications
DST TO TL 07	Design of area efficient and low power 4-bit multiplier based on full- swing gdi technique
DST TO TL 08	Designing efficient circuits based on runtime-reconfigurable field-effect transistors
DST TO TL 09	Designing efficient circuits based on runtime-reconfigurable field-effect transistors
DST TO TL 010	Design and characterization of seu hardened circuits for sram-based fpga
DST TO TL 011	Low leakage clock tree with dual-threshold- voltage split input–output repeatersac
DST TO TL 012	Parametric and functional degradation analysis of complete 14-nm finfet sram
DST TO TL 013	Parametric and functional degradation analysis of complete 14-nm finfet sram
DST TO TL 014	A 7t security oriented sram bitcell
DST TO TL 015	A 7t security oriented sram bitcell
DST TO TL 016	A low power and high speed voltage level shifter based on a regulated cross coupled pull up network
DST TO TL 017	Energy efficient single-ended 6t sram for multimedia applications
DST TO TL 018	Hybrid logical effort for hybrid logic style full adders in multistage structures
DST TO TL 019	Hybrid logical effort for hybrid logic style full adders in multistage structures
DST TO TL 020	Analysis of 1- bit full adder using different techniques in cadence 45nm technology
DST TO TL 021	Seda – single exact dual approximate adders for approximate processors
DST TO TL 022	Analysis of adiabatic flip-flops for ultra low power applications
DST TO TL 023	Power-delay-product, area and threshold-loss analysis of cmos full adder circuits
DST TO TL 024	Power reduction in domino logic using clock gating in 16nm cmos technology
DST TO TL 025	Power efficient design of adiabatic approach for low power vlsi circuits
DST TO TL 026	Low power approximate unsigned divider design using gate diffusion input logic
DST TO TL 027	Design of swing dependent xor-xnor gates based hybrid full adder