VLSI PROJECTS (2019-20)
Design for Testability
| S.NO | TITLES | Download |
| DST TO DT 01 | A high performance scan flip-flop design for serial and mixed mode scan test | |
| DST TO DT 02 | Automatic test pattern generation for timing verification and delay testing of rsfq circuits | |
| DST TO DT 03 | On-chip self-test methodology with all deterministic compressed test patterns recorded in scan chains | |
| DST TO DT 04 | A low-power parallel architecture for linear feedback shift registers | |
| DST TO DT 05 | Efficient design-for-test approach for networks-on-chip | |
| DST TO DT 06 | Modified dual-clcg method and its vlsi architecture for pseudorandom bit generation | |
| DST TO DT 07 | Fpga-based true random number generation using programmable delays in oscillator-rings | |
| DST TO DT 08 | Fpga-based true random number generation using programmable delays in oscillator-rings | |
| DST TO DT 09 | A lightweight lfsr-based strong physical unclonable function design on fpga | |
| DST TO DT 010 | Application-dependent testing of fpga interconnect network | |
| DST TO DT 011 | Multistage linear feedback shift register counters with reduced decoding logic in 130-nm cmos for large-scale array applications |
