Vlsi backend Be
Branch: VLSI
Topic: VLSI BACKEND BE
| S.NO | TITLES | DOWNLOAD |
| FRONTEND | ||
| DST TO C 01 | Approximate Quaternary Addition with the Fast Carry Chains of FPGAs | |
| DST TO C 02 | A Low-Power Configurable Adder for Approximate Applications | |
| DST TO C 03 | A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design | |
| DST TO C 04 | Optimizing Power-Accuracy trade-off in Approximate Adders | |
| DST TO C 05 | A Simple Yet Efficient Accuracy- Configurable Adder Design | |
| DST TO C 06 | A Low Power CMOS Temperature Sensor Frontend for RFID Tags | |
| DST TO C 07 | Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability | |
| DST TO C 08 | A Low-Power Yet High-Speed Configurable Adder for Approximate Computing | |
| DST TO C 09 | Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error- Tolerant Applications | |
| DST TO C 010 | Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications | |
| DST TO C 011 | A Double Error Correction Code for 32-bit Data Words with Efficient Decoding | |
| DST TO C 012 | An Efficient VLSI Architecture for Convolution Based DWT Using MAC | |
| DST TO C 013 | High Speed Power Efficient Carry Select Adder Design | |
| DST TO C 014 | Design of Majority Logic (ML) Based Approximate Full Adders | |
| DST TO C 015 | High Performance VLSI Architecture for Transpose Form FIR Filter using Integrated Module | |
| DST TO C 016 | Fault-tolerant design and analysis of QCA based circuits | |
| DST TO C 017 | Unbiased Rounding for HUB Floating-point Addition | |
| DST TO C 018 | Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error | |
| DST TO C 019 | Combined Pseudo-Exhaustive and Deterministic Testing of Array Multipliers | |
| DST TO C 020 | Nonlinear Binary Codes and Their Utilization for Test | |
| DST TO C 021 | A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher | |
| DST TO C 022 | A Novel approach for design of Real Time Traffic Control System using Verilog HDL | |
| DST TO C 023 | An efficient way of implementing high speed 4-Bit advanced multipliers in FPGA | |
| DST TO C 024 | An Inter-Layer Interconnect BIST Solution for Monolithic 3D ICs | |
| DST TO C 025 | Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications | |
| DST TO C 026 | Built-in Test for Hidden Delay Faults | |
| DST TO C 027 | Design and Verilog HDL Implementation of Carry Skip Adder Using Kogge-Stone Tree Logic | |
| DST TO C 028 | High Speed Efficient Multiplier Design using Reversible Gates | |
| DST TO C 029 | High-Performance NTT Architecture for Large Integer Multiplication | |
| DST TO C 030 | Inexact Arithmetic Circuits for Energy Efficient loT Sensors Data Processing | |
| DST TO C 031 | A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test | |
| DST TO C 032 | A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits | |
| DST TO C 033 | Automotive functional safety assurance by post with sequential observation | |
| DST TO C 034 | Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation | |
| DST TO C 035 | Logic BIST with Capture-per-Clock Hybrid Test Points | |
| DST TO C 036 | Flexible Architecture of Memory BISTs | |
| DST TO C 037 | Efficient Implementations of 4-Bit Burst Error Correction for Memories | |
| DST TO C 038 | Towards Efficient Modular Adders based on Reversible Circuits | |
| DST TO C 039 | Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder | |
| DST TO C 040 | Design, Implementation and Verification of 32-Bit ALU with VIO | |
| DST TO C 041 | All Optical Design of Hybrid Adder Circuit Using Terahertz Optical Asymmetric Demultiplexer | |
| DST TO C 042 | A Novel Reversible Synthesis of Array Multiplier | |
| DST TO C 043 | Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter | |
| DST TO C 044 | FIR filter design based on FPGA | |
| DST TO C 045 | An Approach to LUT Based Multiplier for Short Word Length DSP Systems | |
| DST TO C 046 | FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications | |
| DST TO C 047 | Chip Design for Turbo Encoder Module for In-Vehicle System | |
| DST TO C 048 | BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA | |
| DST TO C 049 | A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA) | |
| DST TO C 050 | Application of Bit-Serial Arithmetic Units for FPGA Implementation of Convolutional Neural Networks | |
| DST TO C 051 | Design and simulation of CRC encoder and decoder using VHDL/verilog | |
| DST TO C 052 | Time to Digital Converter Based on a Ring Oscillator with Even Number of Non- Inverting Elements | |
| DST TO C 053 | A Channel-Sharable Built-In Self-Test Scheme for Multi-Channel DRAMs | |
| DST TO C 054 | Random Number Generation with LFSR Based Stream Cipher Algorithms | |
| DST TO C 055 | Characterization of Clock Buffers for On-Chip Inter-Circuit Communication in Xilinx FPGAs | |
| DST TO C 056 | Design and Implementation of the Algorithm for RB Multiplication to Derive High-Throughput Digit-Serial Multipliers | |
| DST TO C 057 | FPGA Realization of Speech Encryption Based on Modified Chaotic Logistic Map | |
| DST TO C 058 | VLSI Implementation of Channel Estimation for Millimeter Wave Beam forming Training | |
| DST TO C 059 | Heuristic based Majority/Minority Logic Synthesis for Emerging Technologies | |
| DST TO C 060 | A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation | |
| DST TO C 061 | Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression | |
| DST TO C 062 | A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA using Chisel HCL | |
| DST TO C 063 | Area and Performance Evaluation of Central DMA Controller in Xilinx Embedded FPGA Designs | |
| DST TO C 064 | Design of Low Power Multiplierless Linear-Phase FIR Filters | |
| DST TO C 065 | Algorithm for Constructing Minimal Representations of Multiple-output Boolean Functions in The Reversible Logic Circuits | |
| DST TO C 066 | FPGA Implementation of Matrix-Vector Multiplication Using Xilinx System Generator | |
| DST TO C 067 | Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata | |
| DST TO C 068 | Design of Power and Area Efficient Approximate Multipliers | |
| DST TO C 069 | Low-Power Approximate MAC Unit | |
| DST TO C 070 | Efficient Design-for-Test Approach for Networks-on-Chip | |
| DST TO C 071 | Integrating BIST techniques for on-line SoC testing | |
| DST TO C 072 | A Reliable Strong PUF Based on Switched-Capacitor Circuit | |
| DST TO C 073 | Reducing the Hardware Complexity of a Parallel Prefix Adder | |
| DST TO C 074 | Research and implementation of hardware algorithms for multiplying binary numbers | |
| DST TO C 075 | Division circuits using reversible logic gates | |
| Backend | ||
| DST TO C 01 | Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique | |
| DST TO C 02 | Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates | |
| DST TO C 03 | Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder | |
| DST TO C 04 | Positive Feedback Symmetric Adiabatic Logic against Differential Power Attack | |
| DST TO C 05 | Soft-Error Tolerant Design in Near-Threshold-Voltage Computing | |
| DST TO C 06 | Stateful Memristor-Based Search Architecture | |
| DST TO C 07 | CMOS circuit techniques for Mm –wave communications | |
| DST TO C 08 | Approximate Fully Connected Neural Network Generation | |
| DST TO C 09 | Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique | |
| DST TO C 010 | FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks | |
| DST TO C 011 | Analysis of Optimization Techniques for Low Power VLSI Design | |
| DST TO C 012 | Low Power GDI ALU Design with Mixed Logic Adder Functionality | |
| DST TO C 013 | Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications | |
| DST TO C 014 | Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis | |
| DST TO C 015 | Fractional-Order Differentiators and Integrators with Reduced Circuit Complexity | |
| DST TO C 016 | High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop | |
| DST TO C 017 | A Low-Power High-Speed Comparator for Precise Applications | |
| DST TO C 018 | High-Density SOT-MRAM Based on Shared Bitline Structure | |
| DST TO C 019 | Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM | |
| DST TO C 020 | Enabling Fast Process Variation and Fault Simulation Through Macromodelling of Analog Components | |
| DST TO C 021 | A SEU/MBU Tolerant SRAM Bit Cell Based on Multi-Input Gate | |
| DST TO C 022 | Design of low power magnitude comparator | |
| DST TO C 023 | Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications | |
| DST TO C 024 | High-performance engineered gate transistor-based compact digital circuits | |
| DST TO C 025 | Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation |
INSIGHT
