VLSI based ME/M.tech Projects
VLSI
| PROJECT CODE- | PROJECT TITLE | YEAR |
| DST01SV | Area–Delay–Power Efficient Carry-Select Adder | 2014 |
| DST02SV | Shift Register Design Using Two Bit Flip-Flop | 2014 |
| DST03SV | Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells | 2014 |
| DST04SV | Design and Analysis of Approximate Compressors for Multiplication | 2014 |
| DST05SV | High Speed Vedic Multiplier Designs-A Review | 2014 |
| DST06SV | Efficient Integer DCT Architectures for HEVC | 2014 |
| DST07SV | SDR – Implementation Of Low Frequency Trans-Receiver On FPGA | 2014 |
| DST08SV | Design of Dedicated Reversible Quantum Circuitry for Square Computation | 2014 |
| DST09SV | ASIC Design of Reversible Multiplier Circuit | 2014 |
| DST10SV | High throughput pipelined 2D Discrete cosine transform for video compression | 2014 |
| DST11SV | Multiplication Acceleration Through Quarter Precision Wallace Tree Multiplier | 2014 |
| DST12SV | Power Evaluation of Sobel Filter on Xilinx Platform | 2014 |
| DST13SV | FPGA Based Implementation & Power Analysis of Parameterized Walsh Sequences | 2014 |
| DST14SV | A 1-GHz Direct Digital Frequency Synthesizer in an FPGA | 2014 |
| DST15SV | Realization of 2:4 reversible decoder and its applications | 2014 |
| DST16SV | On The Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays | 2014 |
| DST17SV | Low-Complexity Low-Latency Architecture for Matching of Data EncodedWith Hard Systematic Error-Correcting Codes | 2014 |
| DST18SV | Radix-2r Arithmetic for Multiplication by a Constant | 2014 |
| DST19SV | Low power Square and Cube Architectures Using Vedic Sutras | 2014 |
| DST20SV | A Novel Parallel Multiplier for 2’s Complement Numbers Using Booth’s Recoding Algorithm | 2014 |
| DST21SV | 4-2 Compressor Design with New XOR-XNOR Module | 2014 |
| DST22SV | A New Design of Low Power High Speed Hybrid CMOS Full Adder | 2014 |
| DST23SV | Improved design of high-frequency sequential decimal multipliers | 2014 |
| DST24SV | A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter | 2014 |
| DST25SV | FPGA based Partial Reconfigurable FIR Filter Design | 2014 |
| DST26SV | Improved matrix multiplier design for high-speed digital signal processing applications | 2014 |
| DST27SV | An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC | 2014 |
| DST28SV | Power- and Area-Efficient Approximate WallaceTree Multiplier for Error-Resilient Systems | 2014 |
| DST29SV | HDL Based Implementation of NxN Bit-Serial Multiplier | |
| DST30SV | Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay | 2014 |
| DST31SV | Single-Bit Pseudo parallel Processing Low-Oversampling Delta–Sigma Modulator Suitable for SDR Wireless Transmitters | 2014 |
| DST32SV | Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method | 2014 |
| DST33SV | Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating | 2014 |
| DST34SV | Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits | 2014 |
| DST35SV | Mapping Loop Structures onto Parametrized Hardware Pipelines | 2014 |
| DST36SV | Multifunction Residue Architectures for Cryptography | 2014 |
| DST37SV | Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines | 2014 |
| DST38SV | Recursive Approach to the Design of a Parallel Self-Timed Adder | 2014 |
| DST39SV | Two Phase Clocking Subthreshold Adiabatic Logic | 2014 |
| DST40SV | 2-Bit Magnitude Comparator using GDI Technique | 2014 |
| DST41SV | Implementation Of Barrel Shifter using Diode free Adiabatic Logic (DFAL) | 2014 |
| DST42SV | Implementation of Optimized High Performance 4×4 Multiplier using Ancient Vedic Sutra in 45 nm Technology | 2014 |
| DST43SV | Comparative Analysis of Carry Select Adder using 8T and lOT Full Adder Cells | 2014 |
| DST44SV | Design of Low Power Split Path Data Driven Dynamic Ripple Carry Adders | 2014 |
| DST45SV | Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions | 2014 |
| DST46SV | Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count | 2014 |
| DST47SV | Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function | 2014 |
| DST48SV | Design and Simulation of Software Defined Radio Using MATLAB SIMULINK | 2014 |
| DST49SV | FPGA Implementation of Stream Cipher Using Toeplitz Hash Function | 2014 |
| DST50SV | Implementation of Error Correcting methods for asynchronous communication and Modified Completion Detector with reduced area overhead | 2014 |
| DST51TV | Area Delay Power Efficient Carry Select Adder | 2014 |
| DST52TV | On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays | 2014 |
| DST53TV | Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code | 2014 |
| DST54TV | A Method to Extend Orthogonal Latin Square Codes | 2014 |
| DST55TV | Design and Estimation of delay power and area for Parallel prefix adders | 2014 |
| DST56TV | Design and FPGA implementation of compressor based Vedic multiplier | 2014 |
| DST57TV | A Combined SDC SDF Architecture for Normal I/O Pipelined Radix-2 FFT | 2014 |
| DST58TV | Area Delay Efficient Binary Adders in QCA | 2014 |
| DST59TV | Test Versus Security Past and Present | 2014 |
| DST60TV | Skewed Load Test Cubes Based on Functional Broadside Tests for a Low Power Test Set | 2014 |
| DST61TV | High Speed Convolution and De convolution Algorithm | 2014 |
| DST62TV | Fast Radix 10 Multiplication Using Redundant BCD Codes | 2014 |
| DST63TV | Low Complexity Low Latency Architecture for Matching of Data Encoded With Hard Systematic Error Correcting Codes | 2014 |
| DST64TV | Design for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing | 2014 |
| DST65TV | Design of High Performance 64 bit MAC Unit | 2014 |
| DST66TV | Thwarting Scan Based Attacks on Secure-ICs With On-Chip Comparison | 2014 |
| DST67TV | Low Power Test Generation by Merging of Functional Broadside Test Cubes | 2014 |
| DST68TV | Design of Dedicated Reversible Quantum Circuitry for Square Computation | 2014 |
| DST69TV | A Look Ahead Clock Gating Based on Auto Gated Flip Flops | 2014 |
| DST70TV | A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m) | 2014 |
| DST71TV | Aging Aware Reliable Multiplier Design With Adaptive Hold Logic | 2014 |
| DST72TV | An Accuracy Adjustment Fixed Width Booth Multiplier Based on Multilevel Conditional Probability | 2014 |
| DST73TV | Arithmetic Based Binary to RNS Converter Modulo {2n ± k} for jn-Bit Dynamic Range | 2014 |
| DST74TV | Critical Path Analysis and Low Complexity Implementation of the LMS Adaptive Algorithm | 2014 |
| DST75TV | Design Flow for Flip Flop Grouping in Data Driven Clock Gating | 2014 |
| DST76TV | Design of Efficient Binary Comparators in Quantum Dot Cellular Automata | 2014 |
| DST77TV | Efficient Hardware Implementation of Encoder and Decoder for Golay Code | 2014 |
| DST78TV | Efficient Integer DCT Architectures for HEVC | 2014 |
| DST79TV | Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} | 2014 |
| DST80TV | Fault Tolerant Parallel Filters Based on Error Correction Codes | 2014 |
| DST81TV | Low Voltage and Low Power 64-bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure | 2014 |
| DST82TV | On the Design of Efficient Modulo 2n+1 Multiply Add Add Units | 2014 |
| DST83TV | Reverse Converter Design via Parallel Prefix Adders Novel Components Methodology and Implementations | 2014 |
| DST84TV | FPGA based partial reconfigurable fir filter design | 2014 |
| DST85TV | An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation Filter for Multistandard DUC | 2014 |
| DST86KV | An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator | 2014 |
| DST87KV | Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip | 2014 |
| DST88KV | A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits | 2014 |
| DST89KV | Fast Radix-10 Multiplication Using Redundant BCD Codes | 2014 |
| DST90KV | A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values | 2014 |
| DST91KV | Multifunction Residue Architectures for Cryptography | 2014 |
| DST92KV | Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay | 2014 |
| DST93KV | 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler | 2014 |
| DST94KV | Recursive Approach to the Design of a Parallel Self-Timed Adder | 2014 |
| DST95KV | Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications | 2014 |
| DST96KV | Statistical Analysis of MUX-Based Physical Unclonable Functions | 2014 |
| DST97KV | Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme | 2014 |
| DST98KV | Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation | 2014 |
| DST99KV | 2014 | |
| DST100KV | Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm | 2014 |
| DST101KV | A Method to Extend Orthogonal Latin Square Codes | 2014 |
| DST102KV | Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter | 2014 |
| DST103KV | Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator | 2014 |
| DST104KV | On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays | 2014 |
| DST105KV | Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding | 2014 |
| DST106KV | Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic | 2014 |
| DST107KV | Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes | 2014 |
| DST108KV | Area–Delay–Power Efficient Carry-Select Adder | 2014 |
| DST109KV | Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences | 2014 |
| DST110KV | Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement | 2014 |
| DST111KV | Digitally Controlled Pulse Width Modulator for On-Chip Power Management | 2014 |
| DST112KV | Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States | 2014 |
| DST113KV | Area-Delay Efficient Binary Adders in QCA | 2014 |
| DST114KV | Sharing Logic for Built-In Generation of Functional Broadside Tests. | 2014 |
| DST115NV | Pipelined Radix- Feed forward FFT Architectures | 2014 |
| DST116NV | Design, Synthesis and FPGA-based Implementation of a 32-bit Digital Signal Processor | 2014 |
| DST117NV | Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA | 2014 |
| DST118NV | Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support | 2014 |
| DST119NV | Low-Power and Area-Efficient Carry Select Adder | 2014 |
| DST120NV | Scalable Digital CMOS Comparator Using a Parallel Prefix Tree | 2014 |
| DST121NV | Product Code Schemes for Error Correction in MLC NAND Flash Memories | 2014 |
| DST122NV | Efficient Majority Logic Fault Detection WithDifference-Set Codes for Memory Applications | 2014 |
| DST123NV | Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code | 2014 |
| DST124NV | FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer | 2014 |
| DST125NV | VLSI implementation of Fast Addition using Quaternary Signed Digit Number System | 2014 |
| DST126NV | Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG | 2014 |
| DST127NV | Implementation of I2C Master Bus Controller on FPGA | 2014 |
| DST128NV | High Performance Pipelined Design for FFT Processor based on FPGA | 2014 |
| DST129NV | High Performance Hardware Implementation of AES Using Minimal Resources | 2014 |
| DST130NV | Enhanced Area Efficient Architecture for 128 bit Modified CSLA | 2014 |
| DST131NV | Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA | 2014 |
| DST132NV | BIST Based Test Applications Enhanced with Adaptive Low Power RTPG and LFSR Reseeding Techniques | 2014 |
| DST133NV | Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/AccumulationLow-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation | 2014 |
| DST134NV | A NOVEL MODULO ADDER FOR 2n-2k-1 RESIDUE NUMBER SYSTEM | 2014 |
| DST135NV | A VLIW Architecture for Executing Multi-Scalar/Vector Instructions on Unified Datapath | 2014 |
| DST136NV | PARALLEL AES ENCRYPTION ENGINES FOR MANY-CORE PROCESSOR ARRAYS | 2014 |
| DST137NV | A Practical NoC Design for Parallel DES Computation | 2014 |
| DST138NV | Global Built-In Self-Repair for 3D Memories with Redundancy Sharing and Parallel Testing | 2014 |
| DST139NV | Multi operand Redundant Adders on FPGAs | 2014 |
| DST140NV | High-Performance Hardware Implementation for RC4 Stream Cipher | 2014 |
| DST141NV | Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers | 2014 |
| DST142NV | Pipelined Radix- Feed forward FFT Architectures | 2014 |
| DST143NV | LOW-POWER, HIGH-THROUGHPUT, AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC | 2014 |
| DST144NV | Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes | 2014 |
| DST145NV | Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems | 2014 |
| DST146NV | LOW-COMPLEXITY LOW-LATENCY ARCHITECTURE FOR MATCHING OF DATA | 2014 |
| DST147NV | REVERSE CONVERTER DESIGN VIA PARALLEL-PREFIX ADDERS: NOVEL COMPONENTS, METHODOLOGY, AND IMPLEMENTATIONS | 2014 |
| DST148NV | DESIGN OF EFFICIENT BINARY COMPARATORS IN QUANTUM-DOT CELLULAR AUTOMATA | 2014 |
| DST149NV | ENCODEDWITH HARD SYSTEMATIC ERROR-CORRECTING CODES | 2014 |
| DST150NV | BIT-LEVEL OPTIMIZATION OF ADDER-TREES FOR MULTIPLE CONSTANT MULTIPLICATIONS FOR EFFICIENT FIR FILTER IMPLEMENTATION | 2014 |
| DST151NV | EFFICIENT INTEGER DCT ARCHITECTURES FOR HEVC | 2014 |
| DST152NV | FAST SIGN DETECTION ALGORITHM FOR THE RNS MODULI SET {2n+1 − 1, 2n − 1, 2n} | 2014 |
| DST153NV | AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC | 2014 |
| DST154NV | MULTIFUNCTION RESIDUE ARCHITECTURES FOR CRYPTOGRAPHY | 2014 |
| DST155NV | AREA-DELAY-POWER EFFICIENT CARRY-SELECT ADDER | 2014 |
| DST156NV | IMPROVED 8-POINT APPROXIMATE DCT FOR IMAGE AND VIDEO COMPRESSION REQUIRING ONLY 14 ADDITIONS | 2014 |
| DST157NV | HIGH-THROUGHPUT MULTI STANDARD TRANSFORM CORE SUPPORTING MPEG/H.264/VC-1 USING COMMON SHARING DISTRIBUTED ARITHMETIC | 2014 |
| DST158NV | An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator | 2014 |
| DST159NV | A 16-Core Processor With Shared-Memory and Message-Passing Communications | 2014 |
| DST160NV | 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler | 2014 |
| DST161NV | A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor | 2014 |
| DST162NV | 14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability | 2014 |
| DST163NV | Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison | 2014 |
| DST164NV | Power Efficient Class AB Op-Amps With High and Symmetrical Slew Rate | 2014 |
| DST165NV | Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches | 2014 |
| DST166NV | Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDD min-Aware Dual Supply Voltage Technique | 2014 |
| DST167NV | Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks | 2014 |
| DST168NV | Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme | 2014 |
| DST169NV | Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic | 2014 |
| DST170NV | Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-μm CMOS Technology | 2014 |
| DST171NV | FOUR BIT CMOS FULL ADDER IN SUBMICRON TECHNOLOGY WITH LOW LEAKAGE AND GROUND BOUNCE NOISE REDUCTION | 2014 |
| DST172NV | Efficient Multiternary Digit Adder Design in CNTFET Technology | 2014 |
| DST173NV | Design of Sequential Elements for Low Power Clocking System | 2014 |
| DST174NV | Design of Low Power TPG Using LP-LFSR | 2014 |
| DST175NV | Constant Delay Logic Style | 2014 |
| DST176NV | Comparative Performance Analysis of XOR XNOR Function Based High-Speed CMOS Full Adder Circuits | 2014 |
| DST177NV | Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology | 2014 |
| DST178NV | Carbon Nanotubes Blowing New Life into NP Dynamic CMOS Circuits | 2014 |
| DST179NV | Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay | 2014 |
| DST180NV | Area–Delay–Power Efficient Carry-Select Adder | 2014 |
| DST181NV | Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator | 2014 |
| DST182NV | An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator | 2014 |
| DST183NV | A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65 -nm CMOS | 2014 |
| DST184NV | A Low Power Fault Tolerant Reversible Decoder Using cMOS Transistor | 2014 |
| DST185NV | 14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability | 2014 |
| DST186NV | Design of Low Power TPG Using LP-LFSR | 2014 |
| DST187NV | Low-Power and Area-Efficient Carry Select Adder | 2014 |
| DST188NV | Low-Power Pulse-Triggered Flip-Flop Design with Conditional Pulse-Enhancement Scheme | 2014 |
| DST189NV | Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks | 2014 |
| DST190NV | Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology | 2014 |
| DST191NV | High Performance Hardware Implementation of AES Using Minimal Resources | 2014 |
| DST192NV | Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications | 2014 |
| DST193NV | Global Built-In Self-Repair for 3D Memories with Redundancy Sharing and Parallel Testing | 2014 |
| DST194NV | Constant Delay Logic Style | 2014 |
| DST195NV | Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience – 57 VLSI | |
| DST196NV | Scalable Digital CMOS Comparator using a parallel prefix tree | 2014 |
| DST197NV | constant delay logic Style | 2014 |
| DST198NV | Subthreshold Dual Mode Logic – 56VLSI | 2014 |
| DST199NV | Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression – 55 VLSI | 2014 |
| DST200NV | Soft Error Triggering Criterion Based on Simplified Electrical Model of the SRAM Cell – 54 VLSI | 2014 |
| DST201NV | Scalable Digital CMOS Comparator Using a Parallel Prefix Tree – 53 VLSI | 2014 |
| DST202NV | Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits -VLSI 52 | 2014 |
| DST203NV | Power-Up Sequence Control for MTCMOS Designs – VLSI 51 | 2014 |
| DST204NV | Organic Complementary Logic Circuits and Volatile Memories Integrated on Plastic Foils – VLSI 50 | 2014 |
| DST205NV | Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits – VLSI 49 | 2014 |
| DST206NV | Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks – VLSI 48 | 2014 |
| DST207NV | Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme – vlsi 47 | 2014 |
| DST208NV | Low-Power Digital Signal Processing Using Approximate Adders – VLSI 46 | 2014 |
| DST209NV | Low-Power and Area-Efficient Carry Select Adder – 45 | 2014 |
| DST210NV | Low Propagation Delay Load-Balanced 4 × 4SwitchFabricICin0.13-μm CMOS Technology – VLSI 44 | 2014 |
| DST211NV | Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage – VLSI 43 | 2014 |
| DST212NV | Design of Sequential Elements for Low Power Clocking System – VLSI 42 | 2014 |
| DST213NV | Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing – VLSI 41 | 2014 |
| DST214NV | Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating – VLSI 40 | 2014 |
| DST215NV | Constant Delay Logic Style – VLSI 39 | 2014 |
| DST216NV | Comparison of Static and Dynamic Printed Organic Shift Registers – VLSI 38 | 2014 |
| DST217NV | Asynchronous Fine-Grain Power-Gated Logic – VLSI 37 | 2014 |
| DST218NV | Area Efficient ROM-Embedded SRAM Cache – VLSI 36 | 2014 |
| DST219NV | Analysis and Design of a Low-Voltage Low-PowerDouble-Tail Comparator – VLSI 35 | 2014 |
| DST220NV | An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM – VLSI 34 | 2014 |
| DST221NV | A Wide-Range PLL Using Self-Healing Prescaler OR VCO in 65-nm CMOS – VLSI 33 | 2014 |
| DST222NV | A Low-Power Single-Phase Clock Multiband Flexible Divider – VLSI 32 | 2014 |
| DST223NV | A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor – VLSI 31 | 2014 |
| DST224NV | A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop – VLSI 30 | 2014 |
| DST225NV | A 7.65-mW 5-bit 90-nm 1-Gs Folded Interpolated ADC Without Calibration – VLSI 29 | 2014 |
| DST226NV | 16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder – VLSI 28 | 2014 |
| DST227NV | Implementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix-MVC15 | 2014 |
| DST228NV | VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog-MVD16 | 2014 |
| DST229NV | Design a DSP Operations using Vedic Mathematics-Design a DSP Operations using Vedic Mathematics-MVD5 | 2014 |
| DST230NV | VLSI Based Robust Router Architecture-MVC5 | 2014 |
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