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Core VLSI

 

Branch: ELECTRONICS COMMUNICATION

Topic: CORE VLSI (2018-19)

S.No

 

TITLES

 

DOMAIN DOWNLOAD
CORE VLSI

 

DST TO C 01 Approximate Quaternary Addition with the Fast Carry Chains of FPGAs CORE VLSI

 

DST TO C 02 A Low-Power Configurable Adder for Approximate Applications CORE VLSI

 

DST TO C 03 A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design CORE VLSI

 

DST TO C 04 A Low-Power Yet High-Speed Configurable Adder for Approximate Computing CORE VLSI

 

DST TO C 05 A Simple Yet Efficient Accuracy- Configurable Adder Design CORE VLSI

 

DST TO C 06 Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design CORE VLSI

 

DST TO C 07 Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers CORE VLSI

 

DST TO C 08 A Cost-Effective Self-Healing Approach for Reliable Hardware Systems CORE VLSI

 

DST TO C 09 Approximate Sum-of-Products Designs Based on Distributed Arithmetic CORE VLSI

 

DST TO C 010 Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications CORE VLSI

 

DST TO C 011 Design, Evaluation and Application of Approximate High-Radix Dividers CORE VLSI

 

DST TO C 012 Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors CORE VLSI

 

DST TO C 013 Enhancing Fundamental Energy Limits of Field-Coupled Nano computing Circuits CORE VLSI

 

DST TO C 014 Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors CORE VLSI

 

DST TO C 015 Inexact Arithmetic Circuits for Energy Efficient IOT Sensors Data Processing CORE VLSI

CORE VLSI

 

DST TO C 016 Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability CORE VLSI

 

DST TO C 017 Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system CORE VLSI

 

DST TO C 018 On the Difficulty of Inserting Trojans in Reversible Computing Architectures CORE VLSI

 

DST TO C 019 Optimizing Power-Accuracy trade-off in Approximate Adders CORE VLSI

 

DST TO C 020 Power Efficient Approximate Booth Multiplier CORE VLSI

 

DST TO C 021 Reducing the Hardware Complexity of a Parallel Prefix Adder CORE VLSI

 

DST TO C 022 Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder CORE VLSI

 

DST TO C 023 Towards Efficient Modular Adders based on Reversible Circuits CORE VLSI

 

DST TO C 015 A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier CORE VLSI

 

DST TO C 025 Research and implementation of hardware algorithms for multiplying binary numbers CORE VLSI

 

DST TO C 026 Efficient Design for Fixed-Width Adder-Tree CORE VLSI

 

DST TO C 027 Architecture Generator for Type-3 Unum Posit Adder/Sub tractor CORE VLSI

 

COMMUNICATION
DST TO C 01 Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications COMMUNICATION

 

DST TO C 02 A Single and Adjacent Error Correction Code for fast Decoding of Critical Bits COMMUNICATION

 

DST TO C 03 Efficient Implementations of 4-Bit Burst Error Correction for Memories COMMUNICATION

 

DST TO C 04 Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction COMMUNICATION

 

DST TO C 05 Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design COMMUNICATION

 

DST TO C 06 A Double Error Correction Code for 32-bit Data Words with Efficient Decoding COMMUNICATION

 

DST TO C 07 Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields COMMUNICATION

 

DST TO C 08 An Efficient VLSI Architecture for Convolution Based DWT Using MAC COMMUNICATION

 

DST TO C 09 Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method COMMUNICATION

 

DST TO C 010 Reconfigurable Decoder for LDPC and Polar Codes COMMUNICATION

 

DST TO C 011 Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs COMMUNICATION

 

DST TO C 012 Design and simulation of CRC encoder and decoder using VHDL COMMUNICATION

 

DIGITAL SIGNAL PROCESSING
DST TO C 01 An Efficient FPGA Implementation of HEVC Intra Prediction DIGITAL SIGNAL PROCESSING

 

DST TO C 02 An Area Efficient 1015-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators DIGITAL SIGNAL PROCESSING

 

DST TO C 03 Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic DIGITAL SIGNAL PROCESSING

 

Branch: Electronics and Communication

Topic: Embedded Systems(2017-18)

S.no. Project code Project theme Technology Download
1 TODST-CVLSI01 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic CORE VLSI
2 TODST-CVLSI02 A Modified Partial Product Generator for Redundant Binary Multipliers CORE VLSI
3 TODST-CVLSI03 Design & Analysis of 16 bit RISC Processor Using low Power Pipelining CORE VLSI
4 TODST-CVLSI04 Design and Analysis of Approximate Compressors for Multiplication CORE VLSI
5 TODST-CVLSI05 Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics CORE VLSI
6 TODST-CVLSI06 Design and implementation of fast floating point multiplier unit CORE VLSI
7 TODST-CVLSI07 Area and Frequency optimized 1015 point Radix-2 FFT Processor on FPGA CORE VLSI
8 TODST-CVLSI08 Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata CORE VLSI
9 TODST-CVLSI09 Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier CORE VLSI
10 TODST-CVLSI10 Design of Area and Power Efficient Digital FIR Filter Using Modified MAC Unit CORE VLSI
11 TODST-CVLSI11 Design of Low Power and High-Speed Carry Select Adder Using Brent-Kung Adder CORE VLSI
12 TODST-CVLSI12 Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications CORE VLSI
13 TODST-CVLSI13 FPGA Implementation of Scalable Microprogrammed FIR Filter Architectures using Wallace Tree and Vedic Multipliers CORE VLSI
14 TODST-CVLSI14 FPGA Implementation of Vedic Floating Point Multiplier

 

CORE VLSI
15 TODST-CVLSI15 FPGA Realization and Performance Evaluation of Fixed-Width Modified Baugh-Wooley Multiplier CORE VLSI
16 TODST-CVLSI16 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels CORE VLSI
17 TODST-CVLSI17 FPGA based Scalable Fixed Point QRD core using Dynamic Partial Reconfiguration CORE VLSI
18 TODST-CVLSI18 Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA CORE VLSI
19 TODST-CVLSI19 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication CORE VLSI
20 TODST-CVLSI20 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications CORE VLSI
21 TODST-CVLSI21 A High-Speed FPGA Implementation of an RSD-Based ECC Processor CORE VLSI
22 TODST-CVLSI22 Analysis of Ternary Multiplier using Booth Encoding Technique CORE VLSI
23 TODST-CVLSI23 A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM CORE VLSI
15 TODST-CVLSI15 HMFPCC: – Hybrid-Mode Floating Point Conversion Co-processor CORE VLSI
25 TODST-CVLSI25 On the Analysis of Reversible Booth’s Multiplier CORE VLSI
26 TODST-CVLSI26 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding CORE VLSI
27 TODST-CVLSI27 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations CORE VLSI
28 TODST-CVLSI28 Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI CORE VLSI
29 TODST-CVLSI29 Advanced Low Power RISC Processor Design using MIPS Instruction Set CORE VLSI
30 TODST-CVLSI30 RTL Implementation for AMBA ASB APB Protocol at System on Chip Level

 

 

CORE VLSI
31 TODST-CVLSI31 Run-time reconfigurable multi-precision floating point multiplier design for high-speed, low-power applications CORE VLSI
32 TODST-CVLSI32 Technology Optimized Fixed-Point Bit-Parallel Multiplier for LUT-based FPGAs CORE VLSI
33 TODST-CVLSI33 Truncated ternary multipliers CORE VLSI
34 TODST-CVLSI34 An efficient floating point multiplier design for high-speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm CORE VLSI

 

Branch: ELECTRONICS 

Topic: CORE VLSI (2018-19)

S.No

 

TITLES

 

DOMAIN
CORE VLSI

 

DST TO C 01 Approximate Quaternary Addition with the Fast Carry Chains of FPGAs CORE VLSI

 

DST TO C 02 A Low-Power Configurable Adder for Approximate Applications CORE VLSI

 

DST TO C 03 A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design CORE VLSI

 

DST TO C 04 A Low-Power Yet High-Speed Configurable Adder for Approximate Computing CORE VLSI

 

DST TO C 05 A Simple Yet Efficient Accuracy- Configurable Adder Design CORE VLSI

 

DST TO C 06 Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design CORE VLSI

 

DST TO C 07 Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers CORE VLSI

 

DST TO C 08 A Cost-Effective Self-Healing Approach for Reliable Hardware Systems CORE VLSI

 

DST TO C 09 Approximate Sum-of-Products Designs Based on Distributed Arithmetic CORE VLSI

 

DST TO C 010 Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications CORE VLSI

 

DST TO C 011 Design, Evaluation and Application of Approximate High-Radix Dividers CORE VLSI

 

DST TO C 012 Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors CORE VLSI

 

DST TO C 013 Enhancing Fundamental Energy Limits of Field-Coupled Nano computing Circuits CORE VLSI

 

DST TO C 014 Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors CORE VLSI

 

DST TO C 015 Inexact Arithmetic Circuits for Energy Efficient IOT Sensors Data Processing CORE VLSI

CORE VLSI

 

DST TO C 016 Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability CORE VLSI

 

DST TO C 017 Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system CORE VLSI

 

DST TO C 018 On the Difficulty of Inserting Trojans in Reversible Computing Architectures CORE VLSI

 

DST TO C 019 Optimizing Power-Accuracy trade-off in Approximate Adders CORE VLSI

 

DST TO C 020 Power Efficient Approximate Booth Multiplier CORE VLSI

 

DST TO C 021 Reducing the Hardware Complexity of a Parallel Prefix Adder CORE VLSI

 

DST TO C 022 Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder CORE VLSI

 

DST TO C 023 Towards Efficient Modular Adders based on Reversible Circuits CORE VLSI

 

DST TO C 015 A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier CORE VLSI

 

DST TO C 025 Research and implementation of hardware algorithms for multiplying binary numbers CORE VLSI

 

DST TO C 026 Efficient Design for Fixed-Width Adder-Tree CORE VLSI

 

DST TO C 027 Architecture Generator for Type-3 Unum Posit Adder/Sub tractor CORE VLSI

 

COMMUNICATION
DST TO C 01 Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications COMMUNICATION

 

DST TO C 02 A Single and Adjacent Error Correction Code for fast Decoding of Critical Bits COMMUNICATION

 

DST TO C 03 Efficient Implementations of 4-Bit Burst Error Correction for Memories COMMUNICATION

 

DST TO C 04 Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction COMMUNICATION

 

DST TO C 05 Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design COMMUNICATION

 

DST TO C 06 A Double Error Correction Code for 32-bit Data Words with Efficient Decoding COMMUNICATION

 

DST TO C 07 Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields COMMUNICATION

 

DST TO C 08 An Efficient VLSI Architecture for Convolution Based DWT Using MAC COMMUNICATION

 

DST TO C 09 Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method COMMUNICATION

 

DST TO C 010 Reconfigurable Decoder for LDPC and Polar Codes COMMUNICATION

 

DST TO C 011 Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs COMMUNICATION

 

DST TO C 012 Design and simulation of CRC encoder and decoder using VHDL COMMUNICATION

 

DIGITAL SIGNAL PROCESSING
DST TO C 01 An Efficient FPGA Implementation of HEVC Intra Prediction DIGITAL SIGNAL PROCESSING

 

DST TO C 02 An Area Efficient 1015-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators DIGITAL SIGNAL PROCESSING

 

DST TO C 03 Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic DIGITAL SIGNAL PROCESSING

 

Branch: Electronics and Communication

Topic: Embedded Systems(2017-18)

S.no. Project code Project theme Technology Download
1 TODST-CVLSI01 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic CORE VLSI
2 TODST-CVLSI02 A Modified Partial Product Generator for Redundant Binary Multipliers CORE VLSI
3 TODST-CVLSI03 Design & Analysis of 16 bit RISC Processor Using low Power Pipelining CORE VLSI
4 TODST-CVLSI04 Design and Analysis of Approximate Compressors for Multiplication CORE VLSI
5 TODST-CVLSI05 Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics CORE VLSI
6 TODST-CVLSI06 Design and implementation of fast floating point multiplier unit CORE VLSI
7 TODST-CVLSI07 Area and Frequency optimized 1015 point Radix-2 FFT Processor on FPGA CORE VLSI
8 TODST-CVLSI08 Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata CORE VLSI
9 TODST-CVLSI09 Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier CORE VLSI
10 TODST-CVLSI10 Design of Area and Power Efficient Digital FIR Filter Using Modified MAC Unit CORE VLSI
11 TODST-CVLSI11 Design of Low Power and High-Speed Carry Select Adder Using Brent-Kung Adder CORE VLSI
12 TODST-CVLSI12 Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications CORE VLSI
13 TODST-CVLSI13 FPGA Implementation of Scalable Microprogrammed FIR Filter Architectures using Wallace Tree and Vedic Multipliers CORE VLSI
14 TODST-CVLSI14 FPGA Implementation of Vedic Floating Point Multiplier

 

CORE VLSI
15 TODST-CVLSI15 FPGA Realization and Performance Evaluation of Fixed-Width Modified Baugh-Wooley Multiplier CORE VLSI
16 TODST-CVLSI16 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels CORE VLSI
17 TODST-CVLSI17 FPGA based Scalable Fixed Point QRD core using Dynamic Partial Reconfiguration CORE VLSI
18 TODST-CVLSI18 Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA CORE VLSI
19 TODST-CVLSI19 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication CORE VLSI
20 TODST-CVLSI20 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications CORE VLSI
21 TODST-CVLSI21 A High-Speed FPGA Implementation of an RSD-Based ECC Processor CORE VLSI
22 TODST-CVLSI22 Analysis of Ternary Multiplier using Booth Encoding Technique CORE VLSI
23 TODST-CVLSI23 A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM CORE VLSI
15 TODST-CVLSI15 HMFPCC: – Hybrid-Mode Floating Point Conversion Co-processor CORE VLSI
25 TODST-CVLSI25 On the Analysis of Reversible Booth’s Multiplier CORE VLSI
26 TODST-CVLSI26 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding CORE VLSI
27 TODST-CVLSI27 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations CORE VLSI
28 TODST-CVLSI28 Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI CORE VLSI
29 TODST-CVLSI29 Advanced Low Power RISC Processor Design using MIPS Instruction Set CORE VLSI
30 TODST-CVLSI30 RTL Implementation for AMBA ASB APB Protocol at System on Chip Level CORE VLSI
31 TODST-CVLSI31 Run-time reconfigurable multi-precision floating point multiplier design for high-speed, low-power applications CORE VLSI
32 TODST-CVLSI32 Technology Optimized Fixed-Point Bit-Parallel Multiplier for LUT-based FPGAs CORE VLSI
33 TODST-CVLSI33 Truncated ternary multipliers CORE VLSI
34 TODST-CVLSI34 An efficient floating point multiplier design for high-speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm CORE VLSI

 

     


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