Vlsi low power BE

Branch: VLSI

Topic: VLSI LOW POWER BE

 

Sno.	TOPIC	TECH.,	DOWNLOAD
DST TO C 01	An Analog LO Harmonic Suppression Technique for SDR Receivers	VHDL
DST TO C 02	Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator	VHDL
DST TO C 03	Multiloop control for Fast Transient DC-DC Converter	TANNER
DST TO C 04	A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories	VHDL
DST TO C 05	Design of Reconfigurable Digital IF Filter with Low Complexity	VHDL
DST TO C 06	CMOS First Order All Pass Filter with 2 Hz pole Frequency	TANNER
DST TO C 07	Radiation Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Applications	TANNER
DST TO C 08	A High Throughput Hardware Accelerator for Lossless compression of a DDR4 Comand Trace	VHDL
	VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2018
DST TO C 01	Low Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphism Encryption	VHDL
DST TO C 02	Approximate Sum of Products Designs Based on Distributed Arithmetic	VHDL
DST TO C 03	Improving Error Correction Codes for Multiple Cell Upsets in Space Applications	VHDL
DST TO C 04	Low Power and Fast Full Adder by Exploring New XOR and XNOR Gates	VHDL
DST TO C 05	A 12-bit 40-MS/s SAR ADC with a Fast Binary Window DAC Switching Scheme	TANNER
DST TO C 06	Towards Efficient Modular Adders based on Reversible Circuits	TANNER
DST TO C 07	A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS	VHDL
DST TO C 08	Combating Data Leakage Trojans in Commercial and ASIC Applications with Time Division Multiplexing and Random Encoding	TANNER
DST TO C 09	Design of Area Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications	TANNER
DST TO C 010	An Efficient VLSI Architecture for Convolution Based DWT Using MAC	VHDL
DST TO C 011	High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop	TANNER
DST TO C 012	FIR Filter Design Based on FPGA	VHDL
DST TO C 013	Efficient Design for Fixed Width Adder-Tree	VHDL
	VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2017
DST TO C 01	Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers	VHDL
DST TO C 02	RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing	VHDL
DST TO C 03	Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map	VHDL
DST TO C 04	Resource-Efficient SRAM-based Ternary Content Addressable Memory	VHDL
DST TO C 05	Low Power Split Radix FFT Processors using Radix-2 Butterfly Units	VHDL
DST TO C 06	Design of Power and Area Efficient Approximate Multipliers	VHDL
DST TO C 07	Antiwear Leveling Design for SSDs With Hybrid ECC Capability	VHDL
DST TO C 08	Energy Efficient Approximate Multiplier Design using Bit Significance Driven Logic Compression	VHDL/Verilog HDL
DST TO C 09	Low Complexity Methodology for Complex Square Root Computation	VHDL
DST TO C 010	Approximate Error Detection With Stochastic Checkers	VHDL
DST TO C 011	An Efficient Fault Tolerance Design for Integer Parallel Matrix Vector Multiplication	VHDL
DST TO C 012	An ADPLL based PSK Receiver for VHBR 13.56 MHz Contactless Smartcards and NFC Applications	VHDL
DST TO C 013	Low Power High Speed 1-bit Full Adder Circuit design at 45nm CMOS Technology	TANNER
DST TO C 014	Energy Efficient TCAM Search Engine Design Using Priority Decision in Memory Technology	TANNER
DST TO C 015	A Closed Form Expression for Minimum Operating Voltage of CMOS D Flip Flop	TANNER
DST TO C 016	Gate Diffusion input based 4-bit Vedic Multiplier Design	TANNER
DST TO C 017	Efficient Super Resolution Algorithm using Overlapping Bicubic Interpolation	VHDL
DST TO C 018	A Real Time FHD Learning Based Super Resolution System Without a Frame Buffer	VHDL
	VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2016
DST TO C 01	A Single-Ended With Dynamic Feedback Control 8T Sub-threshold SRAM Cell	TANNER
DST TO C 02	OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application	TANNER
DST TO C 03	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects	TANNER
DST TO C 04	Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation	TANNER
DST TO C 05	A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS	TANNER
DST TO C 06	A Fault Tolerance Technique for Combinational Circuits Based on Selective Transistor Redundance	TANNER
DST TO C 07	Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs	TANNER
DST TO C 08	Probability Driven Multibit Flip-Flop Integration with Clock Gating	TANNER
DST TO C 09	A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM	TANNER
DST TO C 010	Designing Tunable Sub-threshold Logic Circuits Using Adaptive Feedback Equalization	TANNER
DST TO C 011	Low-Power Variation-Tolerant Nonvolatile Lookup Table Design	TANNER
DST TO C 012	Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM	TANNER
DST TO C 013	Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators	TANNER
DST TO C 014	High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator	TANNER
DST TO C 015	EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask ControlEMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control	TANNER
DST TO C 016	A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications	TANNER
DST TO C 017	Pre-charge-Free, Low-Power Content-Addressable Memory	TANNER
DST TO C 018	A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications	TANNER
DST TO C 019	A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time, ADC	TANNER
DST TO C 020	Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia	VHDL
DST TO C 021	Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication	VHDL
DST TO C 022	A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography	VHDL
DST TO C 023	High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels	VHDL
DST TO C 024	Graph-Based Transistor Network Generation Method for Super gate Design	MICROWIND
DST TO C 025	Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic	VHDL
DST TO C 026	A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications	VHDL
DST TO C 027	In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers	VHDL
DST TO C 028	Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders	TANNER
DST TO C 029	A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform	VHDL
DST TO C 030	Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals	VHDL
DST TO C 031	HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic	VHDL
DST TO C 032	A High speed and Power Efficient Voltage Level Shifter for Dual Supply Applications	TANNER
DST TO C 033	A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits	VHDL
DST TO C 034	Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops	TANNER
DST TO C 035	Concept, Design, and Implementation of Reconfigurable CORDIC	VHDL
DST TO C 036	Code Compression for Embedded Systems Using Separated Dictionaries	VHDL
DST TO C 037	Source Code Error Detection in High-Level Synthesis Functional Verification	C,VHDL
DST TO C 038	Low-Power FPGA Design Using Memoization-Based Approximate Computing	Verilog HDL
DST TO C 039	A Combined Deblocking Filter and SAO Hardware Architecture for HEVC	Verilog HDL
DST TO C 040	Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding	Verilog HDL
DST TO C 041	RF Power Gating: A Low Power Technique for Adaptive Radios	VHDL
DST TO C 042	VLSI Design of 64bit x 64bit High Performance Multiplier with Redundant Binary Encoding	VHDL
DST TO C 043	Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm	VHDL
DST TO C 044	An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2^k, 2^p-1}	VHDL
DST TO C 045	A 65-nm CMOS Constant Current Source With Reduced PVT Variation	TANNER
DST TO C 046	Design of a Fully Integrated receiver analog baseband chain for 2.4-GHz Zigbee Applications	TANNER
DST TO C 047	Temporarily Fine Grained Sleep Technique for Near and Subthreshold Parallel Achitectures	TANNER
	VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2015
DST TO C 01	Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array	Verilog
DST TO C 02	Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design	TANNER
DST TO C 03	Pre-Encoded Multipliers Based on Non-Redundant Radix-4Signed-Digit Encoding	VHDL
DST TO C 04	Design and FPGA Implementation of Reconfigurable Linear-Phase Digital Filter with Wide Cutoff Frequency Range and Narrow Transition Bandwidth	VHDL
DST TO C 05	VLSI IMPLEMENTATION OF EFFICIENT IMAGE WATERMARKING ALGORITHM	VHDL
DST TO C 06	Obfuscating DSP Circuits via High-Level Transformations	VHDL
DST TO C 07	Partially Parallel Encoder Architecture for Long Polar Codes	VHDL
DST TO C 08	Fully Reused VLSI Architecture ofFM0/Manchester Encoding Using SOLS Technique for DSRC Applications	VHDL
DST TO C 09	Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks	VHDL
DST TO C 010	A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications	VHDL
DST TO C 011	Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems	VHDL
DST TO C 012	Low-Power and Area-Efficient Shift Register Using Pulsed Latches	TANNER
DST TO C 013	A Low-Power Architecture for the Design of a One-Dimensional Median Filter	VHDL
DST TO C 014	Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations	VHDL
DST TO C 015	Implementation of Sub-threshold Adiabatic Logic for Ultralow-Power Application	MICROWIND
DST TO C 016	Quaternary Logic Lookup Table in Standard CMOS	VHDL/MICROWIND
DST TO C 017	An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis	VHDL
DST TO C 018	A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors	VHDL
DST TO C 019	Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications	VHDL
DST TO C 020	Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications	VHDL
DST TO C 021	Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems	VHDL
DST TO C 022	A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)	VHDL
DST TO C 023	Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic	Verilog