VLSI
| Sno. | TOPIC | TECH., | Download |
| DST TO C 01 | An Analog LO Harmonic Suppression Technique for SDR Receivers | VHDL | |
| DST TO C 02 | Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator | VHDL | |
| DST TO C 03 | Multiloop control for Fast Transient DC-DC Converter | TANNER | |
| DST TO C 04 | A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories | VHDL | |
| DST TO C 05 | Design of Reconfigurable Digital IF Filter with Low Complexity | VHDL | |
| DST TO C 06 | CMOS First Order All Pass Filter with 2 Hz pole Frequency | TANNER | |
| DST TO C 07 | Radiation Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Applications | TANNER | |
| DST TO C 08 | A High Throughput Hardware Accelerator for Lossless compression of a DDR4 Comand Trace | VHDL | |
| VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2018
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| DST TO C 01 | Low Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphism Encryption | VHDL | |
| DST TO C 02 | Approximate Sum of Products Designs Based on Distributed Arithmetic | VHDL | |
| DST TO C 03 | Improving Error Correction Codes for Multiple Cell Upsets in Space Applications | VHDL | |
| DST TO C 04 | Low Power and Fast Full Adder by Exploring New XOR and XNOR Gates | VHDL | |
| DST TO C 05 | A 12-bit 40-MS/s SAR ADC with a Fast Binary Window DAC Switching Scheme | TANNER | |
| DST TO C 06 | Towards Efficient Modular Adders based on Reversible Circuits | TANNER | |
| DST TO C 07 | A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS | VHDL | |
| DST TO C 08 | Combating Data Leakage Trojans in Commercial and ASIC Applications with Time Division Multiplexing and Random Encoding | TANNER | |
| DST TO C 09 | Design of Area Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications | TANNER | |
| DST TO C 010 | An Efficient VLSI Architecture for Convolution Based DWT Using MAC | VHDL | |
| DST TO C 011 | High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop | TANNER | |
| DST TO C 012 | FIR Filter Design Based on FPGA | VHDL | |
| DST TO C 013 | Efficient Design for Fixed Width Adder-Tree | VHDL | |
| VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2017 | |||
| DST TO C 01 | Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers | VHDL | |
| DST TO C 02 | RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing | VHDL | |
| DST TO C 03 | Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map | VHDL | |
| DST TO C 04 | Resource-Efficient SRAM-based Ternary Content Addressable Memory | VHDL | |
| DST TO C 05 | Low Power Split Radix FFT Processors using Radix-2 Butterfly Units | VHDL | |
| DST TO C 06 | Design of Power and Area Efficient Approximate Multipliers | VHDL | |
| DST TO C 07 | Antiwear Leveling Design for SSDs With Hybrid ECC Capability | VHDL | |
| DST TO C 08 | Energy Efficient Approximate Multiplier Design using Bit Significance Driven Logic Compression | VHDL/Verilog HDL | |
| DST TO C 09 | Low Complexity Methodology for Complex Square Root Computation | VHDL | |
| DST TO C 010 | Approximate Error Detection With Stochastic Checkers | VHDL | |
| DST TO C 011 | An Efficient Fault Tolerance Design for Integer Parallel Matrix Vector Multiplication | VHDL | |
| DST TO C 012 | An ADPLL based PSK Receiver for VHBR 13.56 MHz Contactless Smartcards and NFC Applications | VHDL | |
| DST TO C 013 | Low Power High Speed 1-bit Full Adder Circuit design at 45nm CMOS Technology | TANNER | |
| DST TO C 014 | Energy Efficient TCAM Search Engine Design Using Priority Decision in Memory Technology | TANNER | |
| DST TO C 015 | A Closed Form Expression for Minimum Operating Voltage of CMOS D Flip Flop | TANNER | |
| DST TO C 016 | Gate Diffusion input based 4-bit Vedic Multiplier Design | TANNER | |
| DST TO C 017 | Efficient Super Resolution Algorithm using Overlapping Bicubic Interpolation | VHDL | |
| DST TO C 018 | A Real Time FHD Learning Based Super Resolution System Without a Frame Buffer | VHDL | |
| VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2016
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| DST TO C 01 | A Single-Ended With Dynamic Feedback Control 8T Sub-threshold SRAM Cell | TANNER | |
| DST TO C 02 | OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application | TANNER | |
| DST TO C 03 | A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects | TANNER | |
| DST TO C 04 | Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation | TANNER | |
| DST TO C 05 | A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS | TANNER | |
| DST TO C 06 | A Fault Tolerance Technique for Combinational Circuits Based on Selective Transistor Redundance | TANNER | |
| DST TO C 07 | Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs | TANNER | |
| DST TO C 08 | Probability Driven Multibit Flip-Flop Integration with Clock Gating | TANNER | |
| DST TO C 09 | A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM | TANNER | |
| DST TO C 010 | Designing Tunable Sub-threshold Logic Circuits Using Adaptive Feedback Equalization | TANNER | |
| DST TO C 011 | Low-Power Variation-Tolerant Nonvolatile Lookup Table Design | TANNER | |
| DST TO C 012 | Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM | TANNER | |
| DST TO C 013 | Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators | TANNER | |
| DST TO C 014 | High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator | TANNER | |
| DST TO C 015 | EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask ControlEMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control | TANNER | |
| DST TO C 016 | A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications | TANNER | |
| DST TO C 017 | Pre-charge-Free, Low-Power Content-Addressable Memory | TANNER | |
| DST TO C 018 | A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications | TANNER | |
| DST TO C 019 | A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time, ADC | TANNER | |
| DST TO C 020 | Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia | VHDL | |
| DST TO C 021 | Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication | VHDL | |
| DST TO C 022 | A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography | VHDL | |
| DST TO C 023 | High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels | VHDL | |
| DST TO C 024 | Graph-Based Transistor Network Generation Method for Super gate Design | MICROWIND | |
| DST TO C 025 | Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic | VHDL | |
| DST TO C 026 | A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications | VHDL | |
| DST TO C 027 | In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers | VHDL | |
| DST TO C 028 | Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders | TANNER | |
| DST TO C 029 | A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform | VHDL | |
| DST TO C 030 | Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals | VHDL | |
| DST TO C 031 | HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic | VHDL | |
| DST TO C 032 | A High speed and Power Efficient Voltage Level Shifter for Dual Supply Applications | TANNER | |
| DST TO C 033 | A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits | VHDL | |
| DST TO C 034 | Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops | TANNER | |
| DST TO C 035 | Concept, Design, and Implementation of Reconfigurable CORDIC | VHDL | |
| DST TO C 036 | Code Compression for Embedded Systems Using Separated Dictionaries | VHDL | |
| DST TO C 037 | Source Code Error Detection in High-Level Synthesis Functional Verification | C,VHDL | |
| DST TO C 038 | Low-Power FPGA Design Using Memoization-Based Approximate Computing | Verilog HDL | |
| DST TO C 039 | A Combined Deblocking Filter and SAO Hardware Architecture for HEVC | Verilog HDL | |
| DST TO C 040 | Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding | Verilog HDL | |
| DST TO C 041 | RF Power Gating: A Low Power Technique for Adaptive Radios | VHDL | |
| DST TO C 042 | VLSI Design of 64bit x 64bit High Performance Multiplier with Redundant Binary Encoding | VHDL | |
| DST TO C 043 | Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm | VHDL | |
| DST TO C 044 | An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2^k, 2^p-1} | VHDL | |
| DST TO C 045 | A 65-nm CMOS Constant Current Source With Reduced PVT Variation | TANNER | |
| DST TO C 046 | Design of a Fully Integrated receiver analog baseband chain for 2.4-GHz Zigbee Applications | TANNER | |
| DST TO C 047 | Temporarily Fine Grained Sleep Technique for Near and Subthreshold Parallel Achitectures | TANNER | |
| VLSI IEEE TRANSACTION – COMPLETED PROJECTS – 2015
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| DST TO C 01 | Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array | Verilog | |
| DST TO C 02 | Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design | TANNER | |
| DST TO C 03 | Pre-Encoded Multipliers Based on Non-Redundant Radix-4Signed-Digit Encoding | VHDL | |
| DST TO C 04 | Design and FPGA Implementation of Reconfigurable Linear-Phase Digital Filter with Wide Cutoff Frequency Range and Narrow Transition Bandwidth | VHDL | |
| DST TO C 05 | VLSI IMPLEMENTATION OF EFFICIENT IMAGE WATERMARKING ALGORITHM | VHDL | |
| DST TO C 06 | Obfuscating DSP Circuits via High-Level Transformations | VHDL | |
| DST TO C 07 | Partially Parallel Encoder Architecture for Long Polar Codes | VHDL | |
| DST TO C 08 | Fully Reused VLSI Architecture ofFM0/Manchester Encoding Using SOLS Technique for DSRC Applications | VHDL | |
| DST TO C 09 | Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks | VHDL | |
| DST TO C 010 | A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications | VHDL | |
| DST TO C 011 | Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems | VHDL | |
| DST TO C 012 | Low-Power and Area-Efficient Shift Register Using Pulsed Latches | TANNER | |
| DST TO C 013 | A Low-Power Architecture for the Design of a One-Dimensional Median Filter | VHDL | |
| DST TO C 014 | Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations | VHDL | |
| DST TO C 015 | Implementation of Sub-threshold Adiabatic Logic for Ultralow-Power Application | MICROWIND | |
| DST TO C 016 | Quaternary Logic Lookup Table in Standard CMOS | VHDL/MICROWIND | |
| DST TO C 017 | An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis | VHDL | |
| DST TO C 018 | A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors | VHDL | |
| DST TO C 019 | Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications | VHDL | |
| DST TO C 020 | Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications | VHDL | |
| DST TO C 021 | Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems | VHDL | |
| DST TO C 022 | A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m) | VHDL | |
| DST TO C 023 | Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic | Verilog |
Branch: Electronics and Communication
Topic: VLSI(2017-18)
| S.no. | Project code | Project theme | Technology | download |
| 1 | ICDST-VLSI01 | Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing | VLSI | |
| 2 | ICDST-VLSI02 | An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC | VLSI | |
| 3 | ICDST-VLSI03 | Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block | VLSI | |
| 4 | ICDST-VLSI04 | High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule | VLSI | |
| 5 | ICDST-VLSI05 | Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks | VLSI | |
| 6 | ICDST-VLSI06 | A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme | VLSI | |
| 7 | ICDST-VLSI07 | Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM | VLSI | |
| 8 | ICDST-VLSI08 | A 65 nm Cryptographic Processor for High Speed Pairing Computation | VLSI | |
| 9 | ICDST-VLSI09 | VLSI Design for SVM-Based Speaker Verification System | VLSI | |
| 11 | ICDST-VLSI11 | 11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids | VLSI | |
| 12 | ICDST-VLSI12 | A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT | VLSI | |
| 13 | ICDST-VLSI13 | A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors | VLSI | |
| 14 | ICDST-VLSI14 | A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks | VLSI | |
| 15 | ICDST-VLSI15 | A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification | VLSI | |
| 16 | ICDST-VLSI16 | A Synergetic Use of Bloom Filters for Error Detection and Correction | VLSI | |
| 17 | ICDST-VLSI17 | A 0.45-V, 14.6-nW CMOS Subthres hold Voltage Reference With No Resistors and No BJTs | VLSI | |
| 18 | ICDST-VLSI18 | An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications | VLSI | |
| 19 | ICDST-VLSI19 | An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats | VLSI | |
| 20 | ICDST-VLSI20 | Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover | VLSI | |
| 21 | ICDST-VLSI21 | Economizing TSV Resources in 3-D Network-on-Chip Design | VLSI | |
| 22 | ICDST-VLSI22 | Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs | VLSI | |
| 23 | ICDST-VLSI23 | Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications | VLSI | |
| 24 | ICDST-VLSI24 | High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels | VLSI | |
| 25 | ICDST-VLSI25 | Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores | VLSI | |
| 26 | ICDST-VLSI26 | Novel VLSI Architecture for Real Time Medical Image Segmentation | VLSI | |
| 27 | ICDST-VLSI27 | Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels | VLSI | |
| 28 | ICDST-VLSI28 | Partially Parallel Encoder Architecture for Long Polar Codes | VLSI | |
| 29 | ICDST-VLSI29 | Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs | VLSI | |
| 30 | ICDST-VLSI30 | Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures | VLSI | |
| 31 | ICDST-VLSI31 | An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs | VLSI | |
| 32 | ICDST-VLSI32 | Drowsy Driver Detection using Representation Learning | VLSI | |
| 33 | ICDST-VLSI33 | Information Hiding as a Challenge for Malware Detection | VLSI | |
| 34 | ICDST-VLSI34 | Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit | VLSI | |
| 35 | ICDST-VLSI35 | Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology | VLSI | |
| 36 | ICDST-VLSI36 | Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication | VLSI | |
| 37 | ICDST-VLSI37 | VLSI Computational Architectures for the Arithmetic Cosine Transform | VLSI | |
| 38 | ICDST-VLSI38 | A New Data Transfer Method via Signal-Rich-Art Code Images Captured by Mobile Devices | VLSI | |
| 39 | ICDST-VLSI39 | A Low-Power Edge Detection Image Sensor Based on Parallel Digital Pulse Computation | VLSI | |
| 40 | ICDST-VLSI40 | WIFI neighbor awareness networking | VLSI | |
| 41 | ICDST-VLSI41 | A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems | VLSI | |
| 42 | ICDST-VLSI42 | A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation | VLSI | |
| 43 | ICDST-VLSI43 | A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation | VLSI | |
| 44 | ICDST-VLSI44 | All Digital Energy Sensing for Minimum Energy Tracking | VLSI | |
| 45 | ICDST-VLSI45 | Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secu re Integrated Circuits | VLSI | |
| 46 | ICDST-VLSI46 | Design of Modified Sec ond-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics | VLSI | |
| 47 | ICDST-VLSI47 | Drowsy Driver Detection using Representation Learning | VLSI | |
| 48 | ICDST-VLSI48 | Energy and Area Efficient Three-Input XOR/ XNORs With Systematic Cell Design Methodology | VLSI | |
| 49 | ICDST-VLSI49 | Fast Design Space Exploration using Vivado HLS: Non-Binary LDPC Decoders | VLSI | |
| 50 | ICDST-VLSI50 | Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint | VLSI | |
| 51 | ICDST-VLSI51 | Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application | VLSI | |
| 52 | ICDST-VLSI52 | Knowledge-Based Neural Network Model for FPGA Logical Architecture Development | VLSI | |
| 53 | ICDST-VLSI53 | Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication | VLSI | |
| 54 | ICDST-VLSI54 | On System-on-Chip Testing Using Hybrid Test Vector Compression | VLSI | |
| 55 | ICDST-VLSI55 | Performance Analysis and Optimization for Homogenous Multi-core System based on 3D Torus Network on Chip | VLSI | |
| 56 | ICDST-VLSI56 | Secure Binary Image Steganography Based on Minimizing the Distortion on the Texture | VLSI | |
| 57 | ICDST-VLSI57 | Star-Type Architecture with Low Transmission Latency for a 2D Mesh NOC | VLSI | |
| 58 | ICDST-VLSI58 | Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product | VLSI | |
| 59 | ICDST-VLSI59 | Unified VLSI architecture for photo core transform used in JPEG XR | VLSI | |
| 60 | ICDST-VLSI60 | A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors | VLSI | |
| 61 | ICDST-VLSI61 | A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator | VLSI | |
| 62 | ICDST-VLSI62 | A Micro-Power Two-Step Incremental Analog-to-Digital Converter | VLSI |
INSIGHT
