VLSI
Branch: VLSI Projects 2018-19
Topic: VLSI
VLSI Projects 2018-19
| S.NO. | Titles | Domain | Download |
| Core VLSI | |||
| DST To V 1 | Approximate Quaternary Addition with the Fast Carry Chains of FPGAs | CORE VLSI | |
| DST To V 2 | A Low-Power Configurable Adder for Approximate Applications | CORE VLSI | |
| DST To V 3 | A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design | CORE VLSI | |
| DST To V 4 | A Low-Power Yet High-Speed Configurable Adder for Approximate Computing | CORE VLSI | |
| DST To V 5 | A Simple Yet Efficient Accuracy- Configurable Adder Design | CORE VLSI | |
| DST To V 6 | Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design | CORE VLSI | |
| DST To V 7 | Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers | CORE VLSI | |
| DST To V 8 | A Cost-Effective Self-Healing Approach for Reliable Hardware Systems | CORE VLSI | |
| DST To V 9 | Approximate Sum-of-Products Designs Based on Distributed Arithmetic | CORE VLSI | |
| DST To V 10 | Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications | CORE VLSI | |
| DST To V 11 | Design, Evaluation and Application of Approximate High-Radix Dividers | CORE VLSI | |
| DST To V 12 | Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors | CORE VLSI | |
| DST To V 13 | Enhancing Fundamental Energy Limits of Field-Coupled Nano computing Circuits | CORE VLSI | |
| DST To V 14 | Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors | CORE VLSI | |
| DST To V 15 | Inexact Arithmetic Circuits for Energy Efficient IOT Sensors Data Processing | CORE VLSI | |
| DST To V 16 | Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability | CORE VLSI | |
| DST To V 17 | Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system | CORE VLSI | |
| DST To V 18 | On the Difficulty of Inserting Trojans in Reversible Computing Architectures | CORE VLSI | |
| DST To V 19 | Optimizing Power-Accuracy trade-off in Approximate Adders | CORE VLSI | |
| DST To V 20 | Power Efficient Approximate Booth Multiplier | CORE VLSI | |
| DST To V 21 | Reducing the Hardware Complexity of a Parallel Prefix Adder | CORE VLSI | |
| DST To V 22 | Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder | CORE VLSI | |
| DST To V 23 | Towards Efficient Modular Adders based on Reversible Circuits | CORE VLSI | |
| DST To V 24 | A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier | CORE VLSI | |
| DST To V 25 | Research and implementation of hardware algorithms for multiplying binary numbers | CORE VLSI | |
| DST To V 26 | Efficient Design for Fixed-Width Adder-Tree | CORE VLSI | |
| DST To V 27 | Architecture Generator for Type-3 Unum Posit Adder/Subtractor | CORE VLSI | |
| Communication | |||
| DST To V 28 | Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications | COMMUNICATION | |
| DST To V 29 | A Single and Adjacent Error Correction Code for fast Decoding of Critical Bits | COMMUNICATION | |
| DST To V 30 | Efficient Implementations of 4-Bit Burst Error Correction for Memories | COMMUNICATION | |
| DST To V 31 | Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction | COMMUNICATION | |
| DST To V 32 | Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design | COMMUNICATION | |
| DST To V 33 | A Double Error Correction Code for 32-bit Data Words with Efficient Decoding | COMMUNICATION | |
| DST To V 34 | Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields | COMMUNICATION | |
| DST To V 35 | An Efficient VLSI Architecture for Convolution Based DWT Using MAC | COMMUNICATION | |
| DST To V 36 | Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method | COMMUNICATION | |
| DST To V 37 | Reconfigurable Decoder for LDPC and Polar Codes | COMMUNICATION | |
| DST To V 38 | Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs | COMMUNICATION | |
| DST To V 39 | Design and simulation of CRC encoder and decoder using VHDL | COMMUNICATION | |
| Digital Signal Processing | |||
| DST To V 40 | An Efficient FPGA Implementation of HEVC Intra Prediction | DIGITAL SIGNAL PROCESSING | |
| DST To V 41 | An Area Efficient 1024-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators | DIGITAL SIGNAL PROCESSING | |
| DST To V 42 | Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic | DIGITAL SIGNAL PROCESSING | |
| DST To V 43 | VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors | DIGITAL SIGNAL PROCESSING | |
| Testing | |||
| DST To V 44 | A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test | TESTING | |
| DST To V 45 | Automotive Functional Safety Assurance by post with Sequential Observation | TESTING | |
| DST To V 46 | Flexible Architecture of Memory BISTs | TESTING | |
| DST To V 47 | Logic BIST with Capture-per-Clock Hybrid Test Points | TESTING | |
| DST To V 48 | Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation | TESTING | |
| Low Power | |||
| DST To V 49 | Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add | LOW POWER | |
| DST To V 50 | Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors | LOW POWER | |
| DST To V 51 | Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences | LOW POWER | |
| Back End | |||
| DST To V 52 | Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique | BACK END | |
| DST To V 53 | Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications | BACK END | |
| DST To V 54 | Design Considerations for Energy-Efficient and VariationTolerant Nonvolatile Logic | BACK END | |
| DST To V 55 | Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators | BACK END | |
| DST To V 56 | Passive Noise Shaping in SAR ADC With Improved Efficiency | BACK END | |
| DST To V 57 | A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm | BACK END | |
| DST To V 58 | Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique | BACK END | |
| DST To V 59 | Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder | BACK END | |
| DST To V 60 | Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates | BACK END | |
| DST To V 61 | Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation | BACK END | |
| DST To V 62 | A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS | BACK END | |
| DST To V 63 | A Droop Measurement Built-in Self-Test Circuit for Digital LowDropout Regulators | BACK END | |
| DST To V 64 | A Highly Efficient Composite Class-AB–AB Miller Op-Amp With High Gain and Stable From 15 pF Up
To Very Large Capacitive Loads |
BACK END | |
| QCA Technology | |||
| DST To V 65 | A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA) | QCA TECHNOLOGY | |
| DST To V 66 | A Novel Five-input Multiple-function QCA Threshold Gate | QCA TECHNOLOGY | |
| DST To V
67 |
An Energy-aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata | QCA TECHNOLOGY | |
| DST To V 68 | An Exact Method for Design Exploration of Quantum-dot Cellular Automata | QCA TECHNOLOGY | |
| DST To V 69 | Design of Majority Logic (ML) Based Approximate Full Adders | QCA TECHNOLOGY | |
| DST To V 70 | Placement and Routing by Overlapping and Merging QCA Gates | QCA TECHNOLOGY |
INSIGHT
