DSP Core
VLSI PROJECTS (2019-20)
DSP Core
| S.NO | TITLES | Download |
| DST TO DSP 01 | An area efficient 1024-point low power radix-22 fft processor with feed-forward multiple delay commutators | |
| DST TO DSP 02 | An area efficient 1024-point low power radix-22 fft processor with feed-forward multiple delay commutators | |
| DST TO DSP 03 | An efficient vlsi architecture for convolution based dwt using mac | |
| DST TO DSP 04 | A 4096-point radix-4 memory-based fft using dsp slices | |
| DST TO DSP 05 | A high-performance and energy-efficient fir adaptive filter using approximate distributed arithmetic circuits | |
| DST TO DSP 06 | A high-performance and energy-efficient fir adaptive filter using approximate distributed arithmetic circuits | |
| DST TO DSP 07 | Efficient implementations of reduced precision redundancy (rpr) multiply and accumulate (mac) | |
| DST TO DSP 08 | Efficient implementations of reduced precision redundancy (rpr) multiply and accumulate (mac) | |
| DST TO DSP 09 | A high-flexible low-latency memory-based fft processor for 4g, wlan, and future 5g | |
| DST TO DSP 010 | A high-flexible low-latency memory-based fft processor for 4g, wlan, and future 5g | |
| DST TO DSP 011 | A theoretical framework for quality estimation and optimization of dsp applications using low-power approximate adders | |
| DST TO DSP 012 | A theoretical framework for quality estimation and optimization of dsp applications using low-power approximate adders | |
| DST TO DSP 013 | Digit-serial versatile multiplier based on a novel block recombination of the modified overlap-free karatsuba algorithm | |
| DST TO DSP 014 | A parallel radix-2k fft processor using single-port merged-bank memory | |
| DST TO DSP 015 | A parallel radix-2k fft processor using single-port merged-bank memory | |
| DST TO DSP 016 | Area delay and energy efficient vlsi architecture for scalable in-place computation of fft on real data | |
| DST TO DSP 017 | Area delay and energy efficient vlsi architecture for scalable in-place computation of fft on real data | |
| DST TO DSP 018 | Feed forward-cut set-free pipe lined multiply–accumulate unit for the machine learning accelerator | |
| DST TO DSP 019 | High performance multiplier less serial pipelined vlsi architecture for real-valued fft | |
| DST TO DSP 020 | Reconfigurable radix-2k×3 feed forward fft architectures | |
| DST TO DSP 021 | Reconfigurable radix-2k×3 feed forward fft architectures | |
| DST TO DSP 022 | A data-flow methodology for accelerating fft | |
| DST TO DSP 023 | An efficient design of 16 bit mac unit using vedic mathematics | |
| DST TO DSP 024 | Low-complexity continuous-flow memory-based fft architectures for real-valued signals |
INSIGHT
