CADENCE ORIENTED

VLSI PROJECTS (2019-20)

Cadence Oriented

S.NO	TITLES	Download
DST TO CO 01	Design of area-efficient and highly reliable rhbd 10t memory cell for aerospace applications
DST TO CO 02	Design of area-efficient and highly reliable rhbd 10t memory cell for aerospace applications
DST TO CO 03	An area efficient 1024-point low power radix-22 fft processor with feed-forward multiple delay commutators
DST TO CO 04	Low-power And Fast Full Adder By Exploring New XOR And XNOR Gates
DST TO CO 05	A Two-speed, Radix-4, Serial–parallel Multiplier
DST TO CO 06	Low-power Approximate Unsigned Multipliers With Configurable Error Recovery
DST TO CO 07	Radiation-hardened 14t SRAM Bitcell With Speed And Power Optimized For Space Application
DST TO CO 08	A very compact cmos analog multiplier for application in cnn synapses
DST TO CO 09	A Two-speed, Radix-4, Serial–parallel Multiplier
DST TO CO 010	A very compact cmos analog multiplier for application in cnn synapses
DST TO CO 011	Designing Efficient Circuits Based On Runtime-reconfigurable Field-effect Transistors
DST TO CO 012	Design And Characterization Of SEU Hardened Circuits For SRAM-based FPGA
DST TO CO 013	Design and analysis of approximate redundant binary multipliers
DST TO CO 014	Parametric And Functional Degradation Analysis Of Complete 14-nm finfet SRAM
DST TO CO 015	Parametric And Functional Degradation Analysis Of Complete 14-nm finfet SRAM
DST TO CO 016	Power Efficient And Reliable Nonvolatile TCAM With Hi-PFO And Semi-complementary Driver
DST TO CO 017	Power Efficient And Reliable Nonvolatile TCAM With Hi-PFO And Semi-complementary Driver
DST TO CO 018	Static Delay Variation Models For Ripple-carry And Borrow-save Adders
DST TO CO 019	Three-dimensional Monolithic finfet-based 8T SRAM Cell Design For Enhanced Read Time And Low Leakage
DST TO CO 020	Tunable Floating-point Adder
DST TO CO 021	A Division-free Toom-cook Multiplication Based Montgomery Modular Multiplication
DST TO CO 022	A Parallel Radix-2k FFT Processor Using Single-port Merged-bank Memory
DST TO CO 023	Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data
DST TO CO 024	A 7t Security Oriented SRAM Bitcell
DST TO CO 025	A 7t Security Oriented SRAM Bitcell
DST TO CO 026	A Data-flow Methodology For Accelerating FFT
DST TO CO 027	An Analysis Of DCM-based True Random Number Generator
DST TO CO 028	A design and implementation of montgomery modular multiplier
DST TO CO 029	Fast & energy efficient binary to bcd converter with complement based logic design (cbld) for bcd multipliers
DST TO CO 030	A 12t Low-power Standard-cell Based SRAM Circuit For Ultra-low-voltage Operations
DST TO CO 031	Analysis Of 1- Bit Full Adder Using Different Techniques In Cadence 45nm Technology
DST TO CO 032	Power-delay-product, Area And Threshold-loss Analysis Of CMOS Full Adder Circuits
DST TO CO 033	Power Reduction In finfet Half Adder Using SVL Technique In 32nm Technology
DST TO CO 034	Delay Optimization Of 4-bit ALU Designed In FS-GDI Technique
DST TO CO 035	Design Of Area Efficient And Low Power 4-bit Multiplier Based On Full Swing GDI Technique
DST TO CO 036	Design of swing dependent xor-xnor gates based hybrid full adder
DST TO CO 037	A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA
DST TO CO 038	Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA
DST TO CO 039	A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA
DST TO CO 040	Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications
DST TO CO 041	Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications