VLSI

ECE  PROJECTS (2020-2021)

S. NO.	TOPIC NAME	DOWNLOAD
DST  VLSI  01	A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
DST  VLSI  02	Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications
DST  VLSI  03	Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms
DST  VLSI  04	TOSAM:AnEnergy-EfficientTruncation-andRounding-BasedScalableApproximate Multiplier
DST  VLSI  05	Design And Analysis Of Approximate Redundant Binary Multipliers.
DST  VLSI  06	Rounding Technique Analysis Of Power-Area & Energy Efficient Approximate Multiplier Design
DST  VLSI  07	A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapath.
DST  VLSI  08	Low Power High Accuracy Approximate Multiplier Using Approximate High Order Compressors.
DST  VLSI  09	Efficient Modular Adder Designs Based on Thermometer & One-Hot Encoding
DST  VLSI  10	Error Detection And Correction In SRAM Emulated TCAMs
DST  VLSI  11	Efficient Design For Fixed Width Adder Tree
DST  VLSI  12	Area –Time Efficient Streaming Architecture For Architecture For FAST And BRIEF Detector
DST  VLSI  13	Hard Ware Efficient Post Processing Architecture For True Random Number Generators
DST  VLSI  14	A Two Speed Radix -4 Serial –Parallel Multiplier
DST  VLSI  15	Low power approximate unsigned multipliers with configurable error recovery
DST  VLSI  16	Energy Quality Scalable Adders Based On Non Zeroing Bit Truncation
DST  VLSI  17	Double MAC On A DSP Boosting The Performance Of Convolutional Neural Networks On FPGAS
DST  VLSI  18	A Low-Power Parallel Architecture for Linear Feedback Shift Registers
DST  VLSI  19	Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems
DST  VLSI  20	Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI technique
DST  VLSI  21	Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications
DST  VLSI  22	Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
DST  VLSI  23	Column selection enabled 10 T SRAM utilizing shared diff VDD WRITE and dropped VDD read for FFT on real data.
DST  VLSI  24	Cell-state-distribution –assisted threshold voltage detector for NAND flash memory
DST  VLSI  25	Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic
DST  VLSI  26	An Approach to LUT Based Multiplier for Short Word Length DSP Systems
DST  VLSI  27	Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system
DST  VLSI  28	FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications
DST  VLSI  29	Unbiased Rounding for HUB Floating-point Addition
DST  VLSI  30	A Low-Power Yet High-Speed Configurable Adder for Approximate Computing
DST  VLSI  31	A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design
DST  VLSI  32	The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA
DST  VLSI  33	Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction
DST  VLSI  34	Efficient Modular Adders based on Reversible Circuits
DST  VLSI  35	MAES: Modified Advanced Encryption Standard for Resource Constraint Environments
DST  VLSI  36	Chip Design for Turbo Encoder Module for In-Vehicle System
DST  VLSI  37	Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
DST  VLSI  38	Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder
DST  VLSI  39	Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis
DST  VLSI  40	Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction
DST  VLSI  41	Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
DST  VLSI  42	An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA
DST  VLSI  43	RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
DST  VLSI  44	DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
DST  VLSI  45	Overloaded CDMA Crossbar for Network-On-Chip
DST  VLSI  46	Design of Power and Area Efficient Approximate Multipliers
DST VLSI   47	Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
DST VLSI   48	Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders.
DST VLSI   49	Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
DST VLSI   50	12T Memory Cell for Aerospace Applications in Nano scale CMOS Technology
DST VLSI   51	Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
DST VLSI   52	Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
DST VLSI   53	Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
DST VLSI   54	A High-Speed FPGA Implementation of an RSD-Based ECC Processor
DST VLSI   55	Hybrid LUT/Multiplexer FPGA Logic Architectures
DST VLSI   56	In-Field Test for Permanent Faults in FIFO Buffers of NOC Routers