ARITHMETIC CORE

VLSI PROJECTS (2019-20)

Arithmetic Core

S.NO	TITLES	Download
DST TO ART 01	A low-power high-speed accuracy-controllable approximate multiplier design
DST TO ART 02	Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications
DST TO ART 03	Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications
DST TO ART 04	Design of approximate radix-4 booth multipliers for error-tolerant computing
DST TO ART 05	Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
DST TO ART 06	A two-speed, radix-4, serial–parallel multiplier
DST TO ART 07	A two-speed, radix-4, serial–parallel multiplier
DST TO ART 08	Low-power approximate unsigned multipliers with configurable error recovery
DST TO ART 09	Tosam: an energy-efficient truncation- and rounding-based scalable approximate multiplier
DST TO ART 010	Tosam: an energy-efficient truncation- and rounding-based scalable approximate multiplier
DST TO ART 011	Analysis, modeling and optimization of equal segment based approximate adders
DST TO ART 012	Analysis, modeling and optimization of equal segment based approximate adders
DST TO ART 013	Block-based carry speculative approximate adder for energy-efficient applications
DST TO ART 014	Efficient implementations of reduced precision redundancy (rpr) multiply and accumulate (mac)
DST TO ART 015	Design methodology to explore hybrid approximate adders for energy-efficient image and video processing accelerators
DST TO ART 016	A combined arithmetic-high-level synthesis solution to deploy partial carry-save radix-8 booth multipliers in datapaths
DST TO ART 017	A combined arithmetic-high-level synthesis solution to deploy partial carry-save radix-8 booth multipliers in datapaths
DST TO ART 018	A theoretical framework for quality estimation and optimization of dsp applications using low-power approximate adders
DST TO ART 019	A theoretical framework for quality estimation and optimization of dsp applications using low-power approximate adders
DST TO ART 020	Concurrent error detectable carry select adder with easy testability
DST TO ART 021	Design and analysis of approximate redundant binary multipliers
DST TO ART 022	Design and analysis of approximate redundant binary multipliers
DST TO ART 023	Digit-serial versatile multiplier based on a novel block recombination of the modified overlap-free karatsuba algorithm
DST TO ART 024	Design methodology to explore hybrid approximate adders for energy-efficient image and video processing accelerators
DST TO ART 025	Design of fsm-based function with reduced number of states in integral stochastic computing
DST TO ART 026	Static delay variation models for ripple-carry and borrow-save adders
DST TO ART 027	Static delay variation models for ripple-carry and borrow-save adders
DST TO ART 028	Tunable floating-point adder
DST TO ART 029	Low-power high-accuracy approximate multiplier using approximate high- order compressors
DST TO ART 030	Machine learning based power efficient approximate 4:2 compressors for imprecise multipliers
DST TO ART 031	Machine learning based power efficient approximate 4:2 compressors for imprecise multipliers
DST TO ART 032	Modified binary multiplier circuit based on vedic mathematics
DST TO ART 033	Performance analysis of wallace tree multiplier with kogge stone adder using 15-4 compressor
DST TO ART 034	Rounding technique analysis for power-area & energy efficient approximate multiplier design
DST TO ART 035	A division-free toom-cook multiplication based montgomery modular multiplication
DST TO ART 036	Fast hub floating-point adder for fpga
DST TO ART 037	Fast hub floating-point adder for fpga
DST TO ART 038	New majority gate based parallel bcd adder designs for quantum-dot cellular automata
DST TO ART 039	16 bit power efficient carry select adder
DST TO ART 040	An efficient design of 16 bit mac unit using vedic mathematics
DST TO ART 041	A design and implementation of montgomery modular multiplier
DST TO ART 042	A hardware-efficient logarithmic multiplier with improved accuracy
DST TO ART 043	A low power binary square rooter using reversible logic
DST TO ART 044	Fast & energy efficient binary to bcd converter with complement based logic design (cbld) for bcd multipliers
DST TO ART 045	Design of delay efficient hybrid adder for high speed applications
DST TO ART 046	Energy efficient speed-independent 64-bit fused multiply-add unit*
DST TO ART 047	Factorized carry look ahead adder
DST TO ART 048	Performance evaluation of fixed-point array multipliers on xilinx fpgas
DST TO ART 049	Implementation of addition and subtraction operations in multiple precision arithmetic
DST TO ART 050	Sensor-based approximate adder design for accelerating error-tolerant and deep-learning applications
DST TO ART 051	A solution to optimize multi-operand adders in cnn architecture on fpga
DST TO ART 052	Design and analysis of majority logic based approximate adders and multipliers
DST TO ART 053	Design and analysis of majority logic based approximate adders and multipliers
DST TO ART 054	Implementation of addition and subtraction operations in multiple precision arithmetic