{"id":935,"date":"2015-01-05T11:24:20","date_gmt":"2015-01-05T11:24:20","guid":{"rendered":"http:\/\/dstarena.com\/blog\/?p=935"},"modified":"2017-01-06T07:42:30","modified_gmt":"2017-01-06T07:42:30","slug":"vlsi-based-me-mtech-project","status":"publish","type":"post","link":"http:\/\/dstarena.com\/blog\/vlsi-based-me-mtech-project\/","title":{"rendered":"VLSI based ME\/M.tech Projects"},"content":{"rendered":"

VLSI<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PROJECT CODE-\u00a0\u00a0\u00a0\u00a0\u00a0 <\/strong><\/td>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 PROJECT TITLE\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 <\/strong><\/td>\nYEAR<\/strong><\/td>\n<\/tr>\n
DST01SV<\/td>\nArea\u2013Delay\u2013Power Efficient Carry-Select Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST02SV<\/td>\nShift Register Design Using Two Bit Flip-Flop<\/td>\n2014<\/td>\n<\/tr>\n
DST03SV<\/td>\nInput Vector Monitoring Concurrent BIST Architecture Using SRAM Cells<\/td>\n2014<\/td>\n<\/tr>\n
DST04SV<\/td>\nDesign and Analysis of Approximate Compressors for Multiplication<\/td>\n2014<\/td>\n<\/tr>\n
DST05SV<\/td>\nHigh Speed Vedic Multiplier Designs-A Review<\/td>\n2014<\/td>\n<\/tr>\n
DST06SV<\/td>\nEfficient Integer DCT Architectures for HEVC<\/td>\n2014<\/td>\n<\/tr>\n
DST07SV<\/td>\nSDR – Implementation Of Low Frequency Trans-Receiver On FPGA<\/td>\n2014<\/td>\n<\/tr>\n
DST08SV<\/td>\nDesign of Dedicated Reversible Quantum Circuitry for Square Computation<\/td>\n2014<\/td>\n<\/tr>\n
DST09SV<\/td>\nASIC Design of Reversible Multiplier Circuit<\/td>\n2014<\/td>\n<\/tr>\n
DST10SV<\/td>\nHigh throughput pipelined 2D Discrete cosine transform for video compression<\/td>\n2014<\/td>\n<\/tr>\n
DST11SV<\/td>\nMultiplication Acceleration Through Quarter Precision Wallace Tree Multiplier<\/td>\n2014<\/td>\n<\/tr>\n
DST12SV<\/td>\nPower Evaluation of Sobel Filter on Xilinx Platform<\/td>\n2014<\/td>\n<\/tr>\n
DST13SV<\/td>\nFPGA Based Implementation & Power Analysis of Parameterized Walsh Sequences<\/td>\n2014<\/td>\n<\/tr>\n
DST14SV<\/td>\nA 1-GHz Direct Digital Frequency Synthesizer in an FPGA<\/td>\n2014<\/td>\n<\/tr>\n
DST15SV<\/td>\nRealization of 2:4 reversible decoder and its applications<\/td>\n2014<\/td>\n<\/tr>\n
DST16SV<\/td>\nOn The Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays<\/td>\n2014<\/td>\n<\/tr>\n
DST17SV<\/td>\nLow-Complexity Low-Latency Architecture for Matching of Data EncodedWith Hard Systematic Error-Correcting Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST18SV<\/td>\nRadix-2r Arithmetic for Multiplication by a Constant<\/td>\n2014<\/td>\n<\/tr>\n
DST19SV<\/td>\nLow power Square and Cube Architectures Using Vedic Sutras<\/td>\n2014<\/td>\n<\/tr>\n
DST20SV<\/td>\nA Novel Parallel Multiplier for 2\u2019s Complement Numbers Using Booth\u2019s Recoding Algorithm<\/td>\n2014<\/td>\n<\/tr>\n
DST21SV<\/td>\n4-2 Compressor Design with New XOR-XNOR Module<\/td>\n2014<\/td>\n<\/tr>\n
DST22SV<\/td>\nA New Design of Low Power High Speed Hybrid CMOS Full Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST23SV<\/td>\nImproved design of high-frequency sequential decimal multipliers<\/td>\n2014<\/td>\n<\/tr>\n
DST24SV<\/td>\nA Decimal \/ Binary Multi-operand Adder using a\u00a0 Fast Binary to Decimal Converter<\/td>\n2014<\/td>\n<\/tr>\n
DST25SV<\/td>\nFPGA based Partial Reconfigurable FIR Filter Design<\/td>\n2014<\/td>\n<\/tr>\n
DST26SV<\/td>\nImproved matrix multiplier design for high-speed digital signal processing applications<\/td>\n2014<\/td>\n<\/tr>\n
DST27SV<\/td>\nAn Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC<\/td>\n2014<\/td>\n<\/tr>\n
DST28SV<\/td>\nPower- and Area-Efficient Approximate WallaceTree Multiplier for Error-Resilient Systems<\/td>\n2014<\/td>\n<\/tr>\n
DST29SV<\/td>\nHDL Based Implementation of NxN Bit-Serial Multiplier<\/td>\n<\/td>\n<\/tr>\n
DST30SV<\/td>\nArea-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay<\/td>\n2014<\/td>\n<\/tr>\n
DST31SV<\/td>\nSingle-Bit Pseudo parallel Processing Low-Oversampling Delta\u2013Sigma Modulator Suitable for SDR Wireless Transmitters<\/td>\n2014<\/td>\n<\/tr>\n
DST32SV<\/td>\nSoftware\/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method<\/td>\n2014<\/td>\n<\/tr>\n
DST33SV<\/td>\nDesign Flow for Flip-Flop Grouping in Data-Driven Clock Gating<\/td>\n2014<\/td>\n<\/tr>\n
DST34SV<\/td>\nGate Mapping Automation for Asynchronous NULL Convention Logic Circuits<\/td>\n2014<\/td>\n<\/tr>\n
DST35SV<\/td>\nMapping Loop Structures onto Parametrized Hardware Pipelines<\/td>\n2014<\/td>\n<\/tr>\n
DST36SV<\/td>\nMultifunction Residue Architectures for Cryptography<\/td>\n2014<\/td>\n<\/tr>\n
DST37SV<\/td>\nLogical Computation on Stochastic Bit Streams with Linear Finite-State Machines<\/td>\n2014<\/td>\n<\/tr>\n
DST38SV<\/td>\nRecursive Approach to the Design of a Parallel Self-Timed Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST39SV<\/td>\nTwo Phase Clocking Subthreshold Adiabatic Logic<\/td>\n2014<\/td>\n<\/tr>\n
DST40SV<\/td>\n2-Bit Magnitude Comparator using GDI Technique<\/td>\n2014<\/td>\n<\/tr>\n
DST41SV<\/td>\nImplementation Of Barrel Shifter using Diode free Adiabatic Logic (DFAL)<\/td>\n2014<\/td>\n<\/tr>\n
DST42SV<\/td>\nImplementation of Optimized High Performance 4×4 Multiplier using Ancient Vedic Sutra in 45 nm Technology<\/td>\n2014<\/td>\n<\/tr>\n
DST43SV<\/td>\nComparative Analysis of Carry Select Adder using 8T and lOT Full Adder Cells<\/td>\n2014<\/td>\n<\/tr>\n
DST44SV<\/td>\nDesign of Low Power Split Path Data Driven Dynamic Ripple Carry Adders<\/td>\n2014<\/td>\n<\/tr>\n
DST45SV<\/td>\nImproved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions<\/td>\n2014<\/td>\n<\/tr>\n
DST46SV<\/td>\nPrecise VLSI Architecture for AI Based 1-D\/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count<\/td>\n2014<\/td>\n<\/tr>\n
DST47SV<\/td>\nEfficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function<\/td>\n2014<\/td>\n<\/tr>\n
DST48SV<\/td>\nDesign and Simulation of Software Defined Radio Using MATLAB SIMULINK<\/td>\n2014<\/td>\n<\/tr>\n
DST49SV<\/td>\nFPGA Implementation of Stream Cipher Using Toeplitz Hash Function<\/td>\n2014<\/td>\n<\/tr>\n
DST50SV<\/td>\nImplementation of Error Correcting methods for asynchronous communication and Modified Completion Detector with reduced area overhead<\/td>\n2014<\/td>\n<\/tr>\n
DST51TV<\/td>\nArea Delay Power Efficient Carry Select Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST52TV<\/td>\nOn the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays<\/td>\n2014<\/td>\n<\/tr>\n
DST53TV<\/td>\nEnhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code<\/td>\n2014<\/td>\n<\/tr>\n
DST54TV<\/td>\nA Method to Extend Orthogonal Latin Square Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST55TV<\/td>\nDesign and Estimation of delay power and area for Parallel prefix adders<\/td>\n2014<\/td>\n<\/tr>\n
DST56TV<\/td>\nDesign and FPGA implementation of compressor based Vedic multiplier<\/td>\n2014<\/td>\n<\/tr>\n
DST57TV<\/td>\nA Combined SDC SDF Architecture for Normal I\/O Pipelined Radix-2 FFT<\/td>\n2014<\/td>\n<\/tr>\n
DST58TV<\/td>\nArea Delay Efficient Binary Adders in QCA<\/td>\n2014<\/td>\n<\/tr>\n
DST59TV<\/td>\nTest Versus Security Past and Present<\/td>\n2014<\/td>\n<\/tr>\n
DST60TV<\/td>\nSkewed Load Test Cubes Based on Functional Broadside Tests for a Low Power Test Set<\/td>\n2014<\/td>\n<\/tr>\n
DST61TV<\/td>\nHigh Speed Convolution and De convolution Algorithm<\/td>\n2014<\/td>\n<\/tr>\n
DST62TV<\/td>\nFast Radix 10 Multiplication Using Redundant BCD Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST63TV<\/td>\nLow Complexity Low Latency Architecture for Matching of Data Encoded With Hard Systematic Error Correcting Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST64TV<\/td>\nDesign for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing<\/td>\n2014<\/td>\n<\/tr>\n
DST65TV<\/td>\nDesign of High Performance 64 bit MAC Unit<\/td>\n2014<\/td>\n<\/tr>\n
DST66TV<\/td>\nThwarting Scan Based Attacks on Secure-ICs With On-Chip Comparison<\/td>\n2014<\/td>\n<\/tr>\n
DST67TV<\/td>\nLow Power Test Generation by Merging of Functional Broadside Test Cubes<\/td>\n2014<\/td>\n<\/tr>\n
DST68TV<\/td>\nDesign of Dedicated Reversible Quantum Circuitry for Square Computation<\/td>\n2014<\/td>\n<\/tr>\n
DST69TV<\/td>\nA Look Ahead Clock Gating Based on Auto Gated Flip Flops<\/td>\n2014<\/td>\n<\/tr>\n
DST70TV<\/td>\nA Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)<\/td>\n2014<\/td>\n<\/tr>\n
DST71TV<\/td>\nAging Aware Reliable Multiplier Design With Adaptive Hold Logic<\/td>\n2014<\/td>\n<\/tr>\n
DST72TV<\/td>\nAn Accuracy Adjustment Fixed Width Booth Multiplier Based on Multilevel Conditional Probability<\/td>\n2014<\/td>\n<\/tr>\n
DST73TV<\/td>\nArithmetic Based Binary to RNS Converter Modulo {2n \u00b1 k} for jn-Bit Dynamic Range<\/td>\n2014<\/td>\n<\/tr>\n
DST74TV<\/td>\nCritical Path Analysis and Low Complexity Implementation of the LMS Adaptive Algorithm<\/td>\n2014<\/td>\n<\/tr>\n
DST75TV<\/td>\nDesign Flow for Flip Flop Grouping in Data Driven Clock Gating<\/td>\n2014<\/td>\n<\/tr>\n
DST76TV<\/td>\nDesign of Efficient Binary Comparators in Quantum Dot Cellular Automata<\/td>\n2014<\/td>\n<\/tr>\n
DST77TV<\/td>\nEfficient Hardware Implementation of Encoder and Decoder for Golay Code<\/td>\n2014<\/td>\n<\/tr>\n
DST78TV<\/td>\nEfficient Integer DCT Architectures for HEVC<\/td>\n2014<\/td>\n<\/tr>\n
DST79TV<\/td>\nFast Sign Detection Algorithm for the RNS Moduli Set {2n+1 \u2212 1, 2n \u2212 1, 2n}<\/td>\n2014<\/td>\n<\/tr>\n
DST80TV<\/td>\nFault Tolerant Parallel Filters Based on Error Correction Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST81TV<\/td>\nLow Voltage and Low Power 64-bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure<\/td>\n2014<\/td>\n<\/tr>\n
DST82TV<\/td>\nOn the Design of Efficient Modulo 2n+1 Multiply Add Add Units<\/td>\n2014<\/td>\n<\/tr>\n
DST83TV<\/td>\nReverse Converter Design via Parallel Prefix Adders Novel Components Methodology and Implementations<\/td>\n2014<\/td>\n<\/tr>\n
DST84TV<\/td>\nFPGA based partial reconfigurable fir filter design<\/td>\n2014<\/td>\n<\/tr>\n
DST85TV<\/td>\nAn Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation Filter for Multistandard DUC<\/td>\n2014<\/td>\n<\/tr>\n
DST86KV<\/td>\nAn Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator<\/td>\n2014<\/td>\n<\/tr>\n
DST87KV<\/td>\nData Encoding Techniques for Reducing Energy Consumption in Network-on-Chip<\/td>\n2014<\/td>\n<\/tr>\n
DST88KV<\/td>\nA Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits<\/td>\n2014<\/td>\n<\/tr>\n
DST89KV<\/td>\nFast Radix-10 Multiplication Using Redundant BCD Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST90KV<\/td>\nA parallel radix-sort-based VLSI architecture for finding the first W maximum\/minimum values<\/td>\n2014<\/td>\n<\/tr>\n
DST91KV<\/td>\nMultifunction Residue Architectures for Cryptography<\/td>\n2014<\/td>\n<\/tr>\n
DST92KV<\/td>\nArea-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay<\/td>\n2014<\/td>\n<\/tr>\n
DST93KV<\/td>\n32 Bit\u00d732 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler<\/td>\n2014<\/td>\n<\/tr>\n
DST94KV<\/td>\nRecursive Approach to the Design of a Parallel Self-Timed Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST95KV<\/td>\nFully Reused VLSI Architecture of FM0\/Manchester Encoding Using SOLS Technique for DSRC Applications<\/td>\n2014<\/td>\n<\/tr>\n
DST96KV<\/td>\nStatistical Analysis of MUX-Based Physical Unclonable Functions<\/td>\n2014<\/td>\n<\/tr>\n
DST97KV<\/td>\nLow-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme<\/td>\n2014<\/td>\n<\/tr>\n
DST98KV<\/td>\nBit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation<\/td>\n2014<\/td>\n<\/tr>\n
DST99KV<\/td>\n<\/td>\n2014<\/td>\n<\/tr>\n
DST100KV<\/td>\nCritical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm<\/td>\n2014<\/td>\n<\/tr>\n
DST101KV<\/td>\nA Method to Extend Orthogonal Latin Square Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST102KV<\/td>\nEfficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter<\/td>\n2014<\/td>\n<\/tr>\n
DST103KV<\/td>\nAnalysis and Design of a Low-Voltage Low-Power Double-Tail Comparator<\/td>\n2014<\/td>\n<\/tr>\n
DST104KV<\/td>\nOn the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays<\/td>\n2014<\/td>\n<\/tr>\n
DST105KV<\/td>\nLow-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding<\/td>\n2014<\/td>\n<\/tr>\n
DST106KV<\/td>\nAging-Aware Reliable Multiplier Design With Adaptive Hold Logic<\/td>\n2014<\/td>\n<\/tr>\n
DST107KV<\/td>\nLow-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST108KV<\/td>\nArea\u2013Delay\u2013Power Efficient Carry-Select Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST109KV<\/td>\nRestoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences<\/td>\n2014<\/td>\n<\/tr>\n
DST110KV<\/td>\nScalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement<\/td>\n2014<\/td>\n<\/tr>\n
DST111KV<\/td>\nDigitally Controlled Pulse Width Modulator for On-Chip Power Management<\/td>\n2014<\/td>\n<\/tr>\n
DST112KV<\/td>\nInput Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States<\/td>\n2014<\/td>\n<\/tr>\n
DST113KV<\/td>\nArea-Delay Efficient Binary Adders in QCA<\/td>\n2014<\/td>\n<\/tr>\n
DST114KV<\/td>\nSharing Logic for Built-In Generation of Functional Broadside Tests.<\/td>\n2014<\/td>\n<\/tr>\n
DST115NV<\/td>\nPipelined Radix- Feed forward FFT Architectures<\/td>\n2014<\/td>\n<\/tr>\n
DST116NV<\/td>\nDesign, Synthesis and FPGA-based Implementation of a 32-bit Digital Signal Processor<\/td>\n2014<\/td>\n<\/tr>\n
DST117NV<\/td>\nDesign and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA<\/td>\n2014<\/td>\n<\/tr>\n
DST118NV<\/td>\nLow-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support<\/td>\n2014<\/td>\n<\/tr>\n
DST119NV<\/td>\nLow-Power and Area-Efficient Carry Select Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST120NV<\/td>\nScalable Digital CMOS Comparator Using a Parallel Prefix Tree<\/td>\n2014<\/td>\n<\/tr>\n
DST121NV<\/td>\nProduct Code Schemes for Error Correction in MLC NAND Flash Memories<\/td>\n2014<\/td>\n<\/tr>\n
DST122NV<\/td>\nEfficient Majority Logic Fault Detection WithDifference-Set Codes for Memory Applications<\/td>\n2014<\/td>\n<\/tr>\n
DST123NV<\/td>\nSoft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code<\/td>\n2014<\/td>\n<\/tr>\n
DST124NV<\/td>\nFPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer<\/td>\n2014<\/td>\n<\/tr>\n
DST125NV<\/td>\nVLSI implementation of Fast Addition using Quaternary Signed Digit Number System<\/td>\n2014<\/td>\n<\/tr>\n
DST126NV<\/td>\nPeriod Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG<\/td>\n2014<\/td>\n<\/tr>\n
DST127NV<\/td>\nImplementation of I2C Master Bus Controller on FPGA<\/td>\n2014<\/td>\n<\/tr>\n
DST128NV<\/td>\nHigh Performance Pipelined Design for FFT Processor based on FPGA<\/td>\n2014<\/td>\n<\/tr>\n
DST129NV<\/td>\nHigh Performance Hardware Implementation of AES Using Minimal Resources<\/td>\n2014<\/td>\n<\/tr>\n
DST130NV<\/td>\nEnhanced Area Efficient Architecture for 128 bit Modified CSLA<\/td>\n2014<\/td>\n<\/tr>\n
DST131NV<\/td>\nDesign and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA<\/td>\n2014<\/td>\n<\/tr>\n
DST132NV<\/td>\nBIST Based Test Applications Enhanced with Adaptive Low Power RTPG and LFSR Reseeding Techniques<\/td>\n2014<\/td>\n<\/tr>\n
DST133NV<\/td>\nLow-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication\/AccumulationLow-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication\/Accumulation<\/td>\n2014<\/td>\n<\/tr>\n
DST134NV<\/td>\nA NOVEL MODULO ADDER FOR 2n-2k-1 RESIDUE NUMBER SYSTEM<\/td>\n2014<\/td>\n<\/tr>\n
DST135NV<\/td>\nA VLIW Architecture for Executing Multi-Scalar\/Vector Instructions on Unified Datapath<\/td>\n2014<\/td>\n<\/tr>\n
DST136NV<\/td>\nPARALLEL AES ENCRYPTION ENGINES FOR MANY-CORE PROCESSOR ARRAYS<\/td>\n2014<\/td>\n<\/tr>\n
DST137NV<\/td>\nA Practical NoC Design for Parallel DES Computation<\/td>\n2014<\/td>\n<\/tr>\n
DST138NV<\/td>\nGlobal Built-In Self-Repair for 3D Memories with Redundancy Sharing and Parallel Testing<\/td>\n2014<\/td>\n<\/tr>\n
DST139NV<\/td>\nMulti operand Redundant Adders on FPGAs<\/td>\n2014<\/td>\n<\/tr>\n
DST140NV<\/td>\nHigh-Performance Hardware Implementation for RC4 Stream Cipher<\/td>\n2014<\/td>\n<\/tr>\n
DST141NV<\/td>\nRadix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers<\/td>\n2014<\/td>\n<\/tr>\n
DST142NV<\/td>\nPipelined Radix- Feed forward FFT Architectures<\/td>\n2014<\/td>\n<\/tr>\n
DST143NV<\/td>\nLOW-POWER, HIGH-THROUGHPUT, AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC<\/td>\n2014<\/td>\n<\/tr>\n
DST144NV<\/td>\nError Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes<\/td>\n2014<\/td>\n<\/tr>\n
DST145NV<\/td>\nEnergy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems<\/td>\n2014<\/td>\n<\/tr>\n
DST146NV<\/td>\nLOW-COMPLEXITY LOW-LATENCY ARCHITECTURE FOR MATCHING OF DATA<\/td>\n2014<\/td>\n<\/tr>\n
DST147NV<\/td>\nREVERSE CONVERTER DESIGN VIA PARALLEL-PREFIX ADDERS: NOVEL COMPONENTS, METHODOLOGY, AND IMPLEMENTATIONS<\/td>\n2014<\/td>\n<\/tr>\n
DST148NV<\/td>\nDESIGN OF EFFICIENT BINARY COMPARATORS IN QUANTUM-DOT CELLULAR AUTOMATA<\/td>\n2014<\/td>\n<\/tr>\n
DST149NV<\/td>\nENCODEDWITH HARD SYSTEMATIC ERROR-CORRECTING CODES<\/td>\n2014<\/td>\n<\/tr>\n
DST150NV<\/td>\nBIT-LEVEL OPTIMIZATION OF ADDER-TREES FOR MULTIPLE CONSTANT MULTIPLICATIONS FOR EFFICIENT FIR FILTER IMPLEMENTATION<\/td>\n2014<\/td>\n<\/tr>\n
DST151NV<\/td>\nEFFICIENT INTEGER DCT ARCHITECTURES FOR HEVC<\/td>\n2014<\/td>\n<\/tr>\n
DST152NV<\/td>\nFAST SIGN DETECTION ALGORITHM FOR THE RNS MODULI SET {2n+1 \u2212 1, 2n \u2212 1, 2n}<\/td>\n2014<\/td>\n<\/tr>\n
DST153NV<\/td>\nAGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC<\/td>\n2014<\/td>\n<\/tr>\n
DST154NV<\/td>\nMULTIFUNCTION RESIDUE ARCHITECTURES FOR CRYPTOGRAPHY<\/td>\n2014<\/td>\n<\/tr>\n
DST155NV<\/td>\nAREA-DELAY-POWER EFFICIENT CARRY-SELECT ADDER<\/td>\n2014<\/td>\n<\/tr>\n
DST156NV<\/td>\nIMPROVED 8-POINT APPROXIMATE DCT FOR IMAGE AND VIDEO COMPRESSION REQUIRING ONLY 14 ADDITIONS<\/td>\n2014<\/td>\n<\/tr>\n
DST157NV<\/td>\nHIGH-THROUGHPUT MULTI STANDARD TRANSFORM CORE SUPPORTING MPEG\/H.264\/VC-1 USING COMMON SHARING DISTRIBUTED ARITHMETIC<\/td>\n2014<\/td>\n<\/tr>\n
DST158NV<\/td>\nAn Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator<\/td>\n2014<\/td>\n<\/tr>\n
DST159NV<\/td>\nA 16-Core Processor With Shared-Memory and Message-Passing Communications<\/td>\n2014<\/td>\n<\/tr>\n
DST160NV<\/td>\n32 Bit\u00d732 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler<\/td>\n2014<\/td>\n<\/tr>\n
DST161NV<\/td>\nA Low Power Fault Tolerant Reversible Decoder Using MOS Transistor<\/td>\n2014<\/td>\n<\/tr>\n
DST162NV<\/td>\n14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability<\/td>\n2014<\/td>\n<\/tr>\n
DST163NV<\/td>\nThwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison<\/td>\n2014<\/td>\n<\/tr>\n
DST164NV<\/td>\nPower Efficient Class AB Op-Amps With High and Symmetrical Slew Rate<\/td>\n2014<\/td>\n<\/tr>\n
DST165NV<\/td>\nNovel Class of Energy-Efficient Very High-Speed Conditional Push\u2013Pull Pulsed Latches<\/td>\n2014<\/td>\n<\/tr>\n
DST166NV<\/td>\nMinimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDD min-Aware Dual Supply Voltage Technique<\/td>\n2014<\/td>\n<\/tr>\n
DST167NV<\/td>\nLow-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks<\/td>\n2014<\/td>\n<\/tr>\n
DST168NV<\/td>\nLow-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme<\/td>\n2014<\/td>\n<\/tr>\n
DST169NV<\/td>\nLow-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic<\/td>\n2014<\/td>\n<\/tr>\n
DST170NV<\/td>\nLow Propagation Delay Load-Balanced 4 \u00d7 4 Switch Fabric IC in 0.13-\u03bcm CMOS Technology<\/td>\n2014<\/td>\n<\/tr>\n
DST171NV<\/td>\nFOUR BIT CMOS FULL ADDER IN SUBMICRON TECHNOLOGY WITH LOW LEAKAGE AND GROUND BOUNCE NOISE REDUCTION<\/td>\n2014<\/td>\n<\/tr>\n
DST172NV<\/td>\nEfficient Multiternary Digit Adder Design in CNTFET Technology<\/td>\n2014<\/td>\n<\/tr>\n
DST173NV<\/td>\nDesign of Sequential Elements for Low Power Clocking System<\/td>\n2014<\/td>\n<\/tr>\n
DST174NV<\/td>\nDesign of Low Power TPG Using LP-LFSR<\/td>\n2014<\/td>\n<\/tr>\n
DST175NV<\/td>\nConstant Delay Logic Style<\/td>\n2014<\/td>\n<\/tr>\n
DST176NV<\/td>\nComparative Performance Analysis of XOR XNOR Function Based High-Speed CMOS Full Adder Circuits<\/td>\n2014<\/td>\n<\/tr>\n
DST177NV<\/td>\nComparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology<\/td>\n2014<\/td>\n<\/tr>\n
DST178NV<\/td>\nCarbon Nanotubes Blowing New Life into NP Dynamic CMOS Circuits<\/td>\n2014<\/td>\n<\/tr>\n
DST179NV<\/td>\nArea-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay<\/td>\n2014<\/td>\n<\/tr>\n
DST180NV<\/td>\nArea\u2013Delay\u2013Power Efficient Carry-Select Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST181NV<\/td>\nAnalysis and Design of a Low-Voltage Low-Power Double-Tail Comparator<\/td>\n2014<\/td>\n<\/tr>\n
DST182NV<\/td>\nAn Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator<\/td>\n2014<\/td>\n<\/tr>\n
DST183NV<\/td>\nA Wide-Range PLL Using Self-Healing Prescaler\/VCO in 65 -nm CMOS<\/td>\n2014<\/td>\n<\/tr>\n
DST184NV<\/td>\nA Low Power Fault Tolerant Reversible Decoder Using cMOS Transistor<\/td>\n2014<\/td>\n<\/tr>\n
DST185NV<\/td>\n14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability<\/td>\n2014<\/td>\n<\/tr>\n
DST186NV<\/td>\nDesign of Low Power TPG Using LP-LFSR<\/td>\n2014<\/td>\n<\/tr>\n
DST187NV<\/td>\nLow-Power and Area-Efficient Carry Select Adder<\/td>\n2014<\/td>\n<\/tr>\n
DST188NV<\/td>\nLow-Power Pulse-Triggered Flip-Flop Design with Conditional Pulse-Enhancement Scheme<\/td>\n2014<\/td>\n<\/tr>\n
DST189NV<\/td>\nLow-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks<\/td>\n2014<\/td>\n<\/tr>\n
DST190NV<\/td>\nComparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology<\/td>\n2014<\/td>\n<\/tr>\n
DST191NV<\/td>\nHigh Performance Hardware Implementation of AES Using Minimal Resources<\/td>\n2014<\/td>\n<\/tr>\n
DST192NV<\/td>\nEfficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications<\/td>\n2014<\/td>\n<\/tr>\n
DST193NV<\/td>\nGlobal Built-In Self-Repair for 3D Memories with Redundancy Sharing and Parallel Testing<\/td>\n2014<\/td>\n<\/tr>\n
DST194NV<\/td>\nConstant Delay Logic Style<\/td>\n2014<\/td>\n<\/tr>\n
DST195NV<\/td>\nTime-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience \u2013 57 VLSI<\/td>\n<\/td>\n<\/tr>\n
DST196NV<\/td>\nScalable Digital CMOS Comparator using a parallel prefix tree<\/td>\n2014<\/td>\n<\/tr>\n
DST197NV<\/td>\nconstant delay logic Style<\/td>\n2014<\/td>\n<\/tr>\n
DST198NV<\/td>\nSubthreshold Dual Mode Logic \u2013 56VLSI<\/td>\n2014<\/td>\n<\/tr>\n
DST199NV<\/td>\nStability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression \u2013 55 VLSI<\/td>\n2014<\/td>\n<\/tr>\n
DST200NV<\/td>\nSoft Error Triggering Criterion Based on Simpli\ufb01ed Electrical Model of the SRAM Cell \u2013 54 VLSI<\/td>\n2014<\/td>\n<\/tr>\n
DST201NV<\/td>\nScalable Digital CMOS Comparator Using a Parallel Pre\ufb01x Tree \u2013 53 VLSI<\/td>\n2014<\/td>\n<\/tr>\n
DST202NV<\/td>\nReactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits -VLSI 52<\/td>\n2014<\/td>\n<\/tr>\n
DST203NV<\/td>\nPower-Up Sequence Control for MTCMOS Designs \u2013 VLSI 51<\/td>\n2014<\/td>\n<\/tr>\n
DST204NV<\/td>\nOrganic Complementary Logic Circuits and Volatile Memories Integrated on Plastic Foils \u2013 VLSI 50<\/td>\n2014<\/td>\n<\/tr>\n
DST205NV<\/td>\nMulti-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits \u2013 VLSI 49<\/td>\n2014<\/td>\n<\/tr>\n
DST206NV<\/td>\nLow-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks \u2013 VLSI 48<\/td>\n2014<\/td>\n<\/tr>\n
DST207NV<\/td>\nLow-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme \u2013 vlsi 47<\/td>\n2014<\/td>\n<\/tr>\n
DST208NV<\/td>\nLow-Power Digital Signal Processing Using Approximate Adders \u2013 VLSI 46<\/td>\n2014<\/td>\n<\/tr>\n
DST209NV<\/td>\nLow-Power and Area-Ef\ufb01cient Carry Select Adder \u2013 45<\/td>\n2014<\/td>\n<\/tr>\n
DST210NV<\/td>\nLow Propagation Delay Load-Balanced 4 \u00d7 4SwitchFabricICin0.13-\u03bcm CMOS Technology \u2013 VLSI 44<\/td>\n2014<\/td>\n<\/tr>\n
DST211NV<\/td>\nIncrease in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage \u2013 VLSI 43<\/td>\n2014<\/td>\n<\/tr>\n
DST212NV<\/td>\nDesign of Sequential Elements for Low Power Clocking System \u2013 VLSI 42<\/td>\n2014<\/td>\n<\/tr>\n
DST213NV<\/td>\nDesign for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing \u2013 VLSI 41<\/td>\n2014<\/td>\n<\/tr>\n
DST214NV<\/td>\nDesign Flow for Flip-Flop Grouping in Data-Driven Clock Gating \u2013 VLSI 40<\/td>\n2014<\/td>\n<\/tr>\n
DST215NV<\/td>\nConstant Delay Logic Style \u2013 VLSI 39<\/td>\n2014<\/td>\n<\/tr>\n
DST216NV<\/td>\nComparison of Static and Dynamic Printed Organic Shift Registers \u2013 VLSI 38<\/td>\n2014<\/td>\n<\/tr>\n
DST217NV<\/td>\nAsynchronous Fine-Grain Power-Gated Logic \u2013 VLSI 37<\/td>\n2014<\/td>\n<\/tr>\n
DST218NV<\/td>\nArea Ef\ufb01cient ROM-Embedded SRAM Cache \u2013 VLSI 36<\/td>\n2014<\/td>\n<\/tr>\n
DST219NV<\/td>\nAnalysis and Design of a Low-Voltage Low-PowerDouble-Tail Comparator \u2013 VLSI 35<\/td>\n2014<\/td>\n<\/tr>\n
DST220NV<\/td>\nAn Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM \u2013 VLSI 34<\/td>\n2014<\/td>\n<\/tr>\n
DST221NV<\/td>\nA Wide-Range PLL Using Self-Healing Prescaler OR VCO in 65-nm CMOS \u2013 VLSI 33<\/td>\n2014<\/td>\n<\/tr>\n
DST222NV<\/td>\nA Low-Power Single-Phase Clock Multiband Flexible Divider \u2013 VLSI 32<\/td>\n2014<\/td>\n<\/tr>\n
DST223NV<\/td>\nA Low Power Fault Tolerant Reversible Decoder Using MOS Transistor \u2013 VLSI 31<\/td>\n2014<\/td>\n<\/tr>\n
DST224NV<\/td>\nA 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop \u2013 VLSI 30<\/td>\n2014<\/td>\n<\/tr>\n
DST225NV<\/td>\nA 7.65-mW 5-bit 90-nm 1-Gs Folded Interpolated ADC Without Calibration \u2013 VLSI 29<\/td>\n2014<\/td>\n<\/tr>\n
DST226NV<\/td>\n16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder \u2013 VLSI 28<\/td>\n2014<\/td>\n<\/tr>\n
DST227NV<\/td>\nImplementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix-MVC15<\/td>\n2014<\/td>\n<\/tr>\n
DST228NV<\/td>\nVLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog-MVD16<\/td>\n2014<\/td>\n<\/tr>\n
DST229NV<\/td>\nDesign a DSP Operations using Vedic Mathematics-Design a DSP Operations using Vedic Mathematics-MVD5<\/td>\n2014<\/td>\n<\/tr>\n
DST230NV<\/td>\nVLSI Based Robust Router Architecture-MVC5<\/td>\n2014<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

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[contact-form to=’ramnath@dstarena.com’ subject=’hello’][contact-field label=’Name’ type=’name’ required=’1’\/][contact-field label=’Email’ type=’email’ required=’1’\/][contact-field label=’College Name’ type=’text’ required=’1’\/][contact-field label=’Contact No’ type=’text’ required=’1’\/][contact-field label=’Your Choice Topic Name’ type=’textarea’ required=’1’\/][\/contact-form]<\/p>\n","protected":false},"excerpt":{"rendered":"

VLSI PROJECT CODE-\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 PROJECT TITLE\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 YEAR DST01SV Area\u2013Delay\u2013Power Efficient Carry-Select Adder 2014 DST02SV Shift Register Design Using Two Bit Flip-Flop 2014 DST03SV Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells 2014 DST04SV Design and Analysis of Approximate Compressors for Multiplication 2014 DST05SV High Speed Vedic Multiplier Designs-A Review 2014 DST06SV Efficient Integer DCT […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[49],"tags":[298,297,296,254,295,294],"class_list":["post-935","post","type-post","status-publish","format-standard","hentry","category-vlsi","tag-best-be-majorminor-training-in-bhopal","tag-latest-m-techphd-thesis-topics","tag-matlab-based-mem-tech-projects","tag-mem-techph-d-thesis-in-bhopal","tag-thesis-topics-based-on-vlsi","tag-vlsi-based-mem-tech-projects"],"aioseo_notices":[],"_links":{"self":[{"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/posts\/935","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/comments?post=935"}],"version-history":[{"count":6,"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/posts\/935\/revisions"}],"predecessor-version":[{"id":3822,"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/posts\/935\/revisions\/3822"}],"wp:attachment":[{"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/media?parent=935"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/categories?post=935"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/dstarena.com\/blog\/wp-json\/wp\/v2\/tags?post=935"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}